AK4648 Datasheet, PDF (55/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
When writing to the IVL7-0 and IVR7-0 bits continuously, the control register should be written with an interval more
than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write
operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is
ignored and zero crossing counter is not reset. Therefore, IVL and IVR can be written with an interval less than zero
crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
Internal IVR
E1H(+30dB)
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
(2)
C6H(+20dB)
Figure 36. IVOL value during ALC operation
(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts.
(2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
by an interval more than zero crossing timeout period after ALC bit = “0”.
MS0625-E-01
- 55 -
2007/06