AK4648 Datasheet, PDF (38/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4648 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits ((x: Don’t care)
Table 14).
Mode
0
1
2
3
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
x
0
1
1024fs
7.35kHz ∼ 13kHz
x
1
0
256fs
7.35kHz ∼ 48kHz
x
1
1
512fs
7.35kHz ∼ 26kHz
(x: Don’t care)
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 15.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or
PMDAC bit = “1”). If MCKI is not provided, the AK4648 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and DAC should be in the
power-down mode (PMADL=PMADR=PMDAC bits = “0”).
AK4648
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 512fs or 1024fs
DSP or μP
MCLK
32fs or 64fs
BCLK
1fs
LRCK
SDTI
SDTO
Figure 23. EXT Master Mode
BCKO bit
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency at Master Mode
MS0625-E-01
- 38 -
2007/06