AK4648 Datasheet, PDF (23/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “↑” to BICK “↑” (Note 46)
tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns
LRCK “↑” to BICK “↓” (Note 47)
tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
−70
-
70
ns
BICK “↓” to SDTO (BCKP bit = “1”)
tBSD
−70
-
70
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
-
ns
Slave Mode
LRCK “↑” to BICK “↑” (Note 46)
tLRB
0.4 x tBCK
-
-
ns
LRCK “↑” to BICK “↓” (Note 47)
BICK “↑” to LRCK “↑” (Note 46)
tLRB
0.4 x tBCK
-
tBLR
0.4 x tBCK
-
-
ns
-
ns
BICK “↓” to LRCK “↑” (Note 47)
tBLR
0.4 x tBCK
-
-
ns
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
-
-
80
ns
BICK “↓” to SDTO (BCKP bit = “1”)
tBSD
-
-
80
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
Audio Interface Timing (Right/Left justified & I²S)
-
ns
Master Mode
BICK “↓” to LRCK Edge (Note 48)
tMBLR
−40
-
40
ns
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
−70
-
70
ns
BICK “↓” to SDTO
tBSD
−70
-
70
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
-
ns
Slave Mode
LRCK Edge to BICK “↑” (Note 48)
tLRB
50
-
-
ns
BICK “↑” to LRCK Edge (Note 48)
tBLR
50
-
-
ns
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
-
80
ns
BICK “↓” to SDTO
tBSD
-
-
80
ns
SDTI Hold Time
tSDH
50
-
-
ns
SDTI Setup Time
tSDS
50
-
-
ns
Note 46. MSBS, BCKP bits = “00” or “11”.
Note 47. MSBS, BCKP bits = “01” or “10”.
Note 48. BICK rising edge must not occur at the same time as LRCK edge.
MS0625-E-01
- 23 -
2007/06