Z8927320VSC Datasheet, PDF (53/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
Inst. Description Synopsis
Operands
Words Cycles Examples
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, <regind>
the <bank switch> defaults to ON.
NEG Negate
NEG <cc>,A
<cc>, A
A
1
1
NEG MI,A
1
1
NEG A
NOP No operation NOP
None
1
1
NOP
OR Bitwise OR OR <dest>,<src> A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
OR A,P0:1
1
1
OR A, D0:1
2
2
OR A,#%2C21
1
3
OR A,@@P2:1+
1
1
OR A, %2C
1
1
OR A,@P1:0–LOOP
1
1
OR A,EXT6
1
1
OR A,#%12
POP Pop value POP <dest>
from stack
<pregs>
<dregs>
<regind>
<hwregs>
1
1
POP P0:0
1
1
POP D0:1
1
1
POP @P0:0
1
1
POP A
PUSH Push value PUSH <src>
onto stack
<pregs>
<dregs>
<regind>
<hwregs>
<limm>
<accind>
<memind>
1
1
PUSH P0:0
1
1
PUSH D0:1
1
1
PUSH @P0:0
1
1
PUSH BUS
2
2
PUSH #12345
1
3
PUSH @A
1
3
PUSH @@P0:0
RET Return from RET
subroutine
None
1
2
RET
RL
Rotate Left RL <cc>,A
<cc>,A
A
1
1
RL NZ,A
1
1
RL A
RR Rotate Right RR <cc>,A
<cc>,A
A
1
1
RR C,A
1
1
RR A
SCF Set C flag SCF
None
1
1
SCF
SIEF Set IE flag SIEF
None
1
1
SIEF
SLL Shift left
SLL
logical
[<cc>,]A
A
1
1
SLL NZ,A
1
1
SLL A
SOPF Set OP flag SOPF
None
1
1
SOPF
SRA Shift right
arithmetic
SRA<cc>,A
<cc>,A
A
1
1
SRA NZ,A
1
1
SRA A
SUB Subtract
SUB<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
SUB A,P1:1
1
1
SUB A,D0:1
2
2
SUB A,#%2C2C
1
3
SUB A,@D0:1
1
1
SUB A,%15
1
1
SUB A,@P2:0–LOOP
1
1
SUB A,STACK
1
1
SUB A, #%12
DS000202-DSP0599
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