Z8927320VSC Datasheet, PDF (38/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
PERIPHERALS
Analog to Digital Converter (A/D)
The A/D is a 4-channel 8-bit half-flash converter. It uses
two reference resistor ladders, one for the upper 5 bits, and
another for the lower 3 bits. Two external reference voltage
input pins, VAHI and VALO, set the input voltage mea-
surement conversion range. The converter is auto-zeroed
prior to each sampling period. Bank13/EXT0 is the A/D
control register.
The conversion time depends on the system clock frequency
and the selection of the A/D prescaler value, bits
DIV2–DIV0. The clock prescaler can be programmed to de-
rive a 2 µs conversion time. For example, when deriving
the A/D clock from a 20-MHz system clock, the A/D pres-
caler value should be set to divide by 40.
Bits ADST1–ADST0 determine one of the following start
conversion options:
• Writing to the ADCTL control register
• ISR1
• C/T2 time-out
• C/T0 time-out
The start conversion operation may begin at any time. If a
conversion is in progress, and a new start conversion signal
is received, the conversion in progress will abort, and a new
conversion will initiate.
Bits QUAD and SCAN determine one of the following
Modes of operation:
• One channel is converted four times, with the results se-
quentially written to result registers 0, 1, 2 and 3.
• One channel is converted one time, with the respective
result register updated.
• Four channels are converted one time each, with the re-
spective four result registers updated.
• Four channels are converted repeatedly, with the respec-
tive four result registers constantly updated.
When one of the two four-channel modes is selected, the
channel specified by CSEL1–CSEL0 will convert first. The
other three channels will convert in sequence. In the se-
quence, AN0 follows AN3.
Bit ADIE enables the A/D to generate interrupts at the end
of a conversion. Bit ADIT determines whether an interrupt
occurs after the first or fourth conversion.
To reduce power consumption the A/D can be disabled by
clearing the ADE bit.
Though the A/D will function with smaller input signals and
reference voltages, the noise and offsets remain constant.
The relative error of the converter will increase and the con-
version time will also take longer.
ISR1
C/T0
C/T2 ADCTL Reg.
AN0
AN1
AN2
AN3
4-Channel
Multiplexer
38
Start
Converter
A/D
Prescaler
Channel Select
Quad
Scan
A/D
Control
Register
Internal
Bus
Sample
and
Hold
Half-Flash
A/D
Converter
Figure 28. ADC Architecture
4x8
Result
Register
DS000202-DSP0599