Z8927320VSC Datasheet, PDF (23/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
SS*
SS-SDO Valid
SS-SCLK Setup
SCLK*
SCLK-SDO Valid
SDO
TRI-STATE
Valid
SDI-SCLK Setup
SDI
Valid
SCLK-SDI Hold
*Notes: The polarity of SCLK and SS are programmable by the user. SS is used in Slave Mode only.
This figure illustrates data transmission on the falling edge of SCLK,
data reception on the rising edge of SCLK, with SS active Low (default).
Figure 15. SPI Timing (Master and Slave Modes)
DS000202-DSP0599
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