Z8927320VSC Datasheet, PDF (33/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
I/O PORTS
I/O pin allocation of ports for the different package types
is designed to provide configuration flexibility. Each port
line of Ports 0, 1, and 2 can be independently selected as
an input or an output. Each port’s output lines can be glo-
bally selected as push-pull or as open-drain outputs
Table 15. I/O Port Bit Allocations
Device Pins
P0 MSB
P0 LSB
P1
P2
P3
44-Pin PLCC,
44-Pin PQFP
ED15–ED8, or
P0.15–P0.8, or
P1.7–P1.0
ED7–ED0, or
P0.7–P0.0
P2.4–P2.0
64-Pin TQFP,
68-Pin PLCC
ED15–ED8, or
P0.15–P0.8
ED7–ED0, or
P0.7–P0.0
P1.7–P1.0
P2.7–P2.0
80-Pin PQFP
ED15–ED8, or
P0.15–P0.8
ED7–ED0, or
P0.7–P0.0
P1.7–P1.0
P2.7–P2.0
P3.7–P3.0
Open-Drain
OEN
Data Out
PAD
Data In
R ≈ 500 kΩ
Auto Latch
Figure 24. Port 0, 1 and 2 Configuration
DS000202-DSP0599
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