Z8927320VSC Datasheet, PDF (34/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
I/O PORTS (Continued)
Port0Ñ16-Bit Programmable I/O
Bank15/EXT0 is the Port0 direction control register.
Bank15/EXT1 includes specific bits to enable and config-
ure Port0. The Port0 data register is Ext4 in Banks 0, 1, or 5.
ZiLOG
Bank 15/Ext 0 Reg
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 25. Port 0 Control Register
Port I/O Direction
0 = Input (default)
1 = Output
Bank 15/EXT1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Allocation of External Data (ED) Bus/Port0 Pins
000 = ED Bus 15-0 (default)
001 = Pins 15–8 ↔ P1.7–P1.0,
Pins 7–0 ↔ ED Bus 7–0
010 = Reserved
011 = Pins 15–8 ↔ P0.15–P08,
Pins 7–0 ↔ ED Bus 7–0
100 = P0.15–P0.0
101 = Pins 15–8 ↔ P1.7–P1.0
Pins 7–0 ↔ P0.7–P0.0
110 = Reserved
111 = Reserved
INT2
0 = Disabled (default)
1 = Enabled
INT1
0 = Disabled (default)
1 = Enabled
CLKOUT
0 = Disabled (default)
1 = Enabled
Port1 Outputs
0 = Push-Pull (default)
1 = Open-Drain
Port0 Outputs
0 = Push-Pull (default)
1 = Open-Drain
Port I/O Output Bit Directions
0 = Input (default)
1 = Output
Figure 26. Bank15/EXT1 Register
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DS000202-DSP0599