Z8927320VSC Datasheet, PDF (21/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
TIMING DIAGRAMS
TCY
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
CPWL
T_r
CPWH
T_f
Figure 10. Clock Timing
RD/WR
DS
EA(2:0)
ED(15:0)
RWSET
RWHOLD
EASET
Valid Address Out
RDSET
Data
Figure 11. Read Timing
EAHOLD
RDHOLD
RD/WR
DS
WAIT
CLKOUT
EA(2:0)
WLAT
ED(15:0)
DS000202-DSP0599
WDEA
Valid Address Out
RDSET
Data
Figure 12. Read Timing Using WAIT Pin
RDHOLD
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