Z8927320VSC Datasheet, PDF (31/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
Interrupt Allocation RegisterÑBank15/EXT6
Bits 3–0 of the Interrupt Allocation Register define which
unique interrupt source the highest priority, and is allocated
to ISR0 (Interrupt Service Request 0).
Bits 7–4 of the Interrupt Allocation Register define which
unique interrupt source has the second highest priority, and
is allocated to ISR1 (Interrupt Service Request 1).
Bits 15–8 of the Interrupt Allocation Register are enable bits
for common interrupt sources which have the lowest prior-
ity, and are all allocated to ISR2 (Interrupt Service Request
2). All the enabled interrupts which are not allocated to ISR0
or ISR1, are allocated to ISR2. When an ISR2 interrupt oc-
curs, the interrupt service routine must read the Interrupt
Status Register in EXT7 to determine the source. The In-
terrupt Status Register can be used for polling interrupts.
An Interrupt that is not selected as a source to ISR0, ISR1,
or ISR2, is disabled.
Bank 15/EXT6
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ISR0 Source (highest priority)
0000 = A/D
0001 = SPI
0010 = C/T0
0011 = C/T1
0100 = C/T2
0101 = INT0
0110 = INT1
0111 = INT2
1xxx = ISR0 Disabled
ISR1 Source (medium priority)
0000 = A/D
0001 = SPI
0010 = C/T0
0011 = C/T1
0100 = C/T2
0101 = INT0
0110 = INT1
0111 = INT2
1xxx = ISR0 Disabled
ISR2 Interrupt Source (lowest priority)
1 = Enable, 0 = Disable
Bit 8 = A/D
Bit 9 = SPI
Bit 10 = C/T0
Bit 11 = C/T1
Bit 12 = C/T2
Bit 13 = INT0
Bit 14 = INT1
Bit 15 = INT2
Figure 21. Interrupt Allocation Register
DS000202-DSP0599
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