Z8927320VSC Datasheet, PDF (28/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
REGISTERS (Continued)
Table 12. RPL Description
S2
S1
S0
Loop Size
0
0
0
256
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
The following are not actually registers, but are read or writ-
ten in the same way as hardware registers on the chip:
Register
BUS
Dn:b
EXTn
Register Definition
D-Bus
Eight Data Pointers
External Register, 16-bit
BUS is a read-only register which, when accessed, returns
the contents of the D-Bus. BUS is used for emulation only.
ZiLOG
Dn:b refers to locations in RAM that can be used as a pointer
to locations in program memory which is efficient for co-
efficient addressing. The programmer decides which loca-
tion to choose from two bits in the status register and two
bits in the operand. Thus, only the lower 16 possible loca-
tions in RAM can be specified. At any one time, there are
eight usable pointers, four per bank, and the four pointers
are in consecutive locations in RAM. For example, if
S3/S4=01 in the status register, then D0:0/D1:0/D2:0/D3:0
refer to register locations 4/5/6/7 in RAM Bank 0. Note that
when the data pointers are being written to, a number is ac-
tually being loaded to Data RAM, so they can be used as a
limited method for writing to RAM.
EXTn are external registers (n = 0 to 6). These are seven
16-bit register addresses provided for mapping internal and
external peripherals into the address space of the processor.
Note that for external peripherals the actual register RAM
does not exist on the chip, but would exist as part of the ex-
ternal device, such as an A/D result latch. The External Ad-
dress Bus, EA2–EA0, the External Data Bus, ED15–ED0,
DS, WAIT, and RD/WR are used to access external periph-
erals.
EXT7 is used for Register Bank Select, and to program wait
states for EXT0–EXT6, and is not available for accessing
an external peripheral.
Negative
Overflow
Zero
Carry
User Input UI1,UI0
(Read Only)
MPY output arithmetically
shifted right by three bits
Overflow Protection
N OV Z C UI1 UI0 SH3 OP IE UO1 UO0
RPL
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Ram
Pointer
000
001
010
011
100
101
110
111
Loop
Size
256
2
4
8
16
32
64
128
"Short Form Direct" bits
User Output UO1, UO0
(Complemented)
Global Interrupt Enable
Figure 19. Status Register
28
DS000202-DSP0599