Z8927320VSC Datasheet, PDF (42/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
PERIPHERALS (Continued)
TPR—Prescaler Register (Bank13,14/EXT5). TPR is an
8-bit down counter that holds the current Prescaler Count
Value. It can be read like any other ordinary register. How-
ever, writing to TPR is different than writing to an ordinary
register. A write to TPR causes the lower 8-bit contents of
TPLR to be written into TPR, causing the Prescaler to be
retriggered.
ZiLOG
7 Bank 13,14/EXT5 0
TPR
8-Bit Counter
Figure 36. TPR—Prescaler Register
15
Bank 13,14/EXT2
0
Timer Reload Value
Figure 33. TMLR—Load Register
15
Bank 13,14/EXT3
0
Timer Register
Figure 34. TMR—Counter Register
Bank 13,14/EXT4
15 14
87
0
Ò1Ó
Zeros
Prescaler
Reload Value
Figure 35. TPLR—Prescaler Load Register
Prescaler Operation
The Prescaler section comprises TPLR and TPR, followed
by a divide-by-two flip-flop. This operation generates a 50
percent duty cycle output, TMCLKIN. TPR’s input clock
is the system clock. The maximum prescaler output fre-
quency is 1/2 the system clock frequency.
After TPR is loaded, it decrements at the system clock fre-
quency and generates an output to the divide-by-two flip-
flop. When the count reaches 0, the TPR counter is reloaded
from the lower 8 bits of TPLR Register.
Two other events cause a reloading of the TPR counter:
1. Writing to TPR
2. Reloading TMR, which happens when TMR under-
flows, or when TMR is written.
Note: For C/T Modes 8–11, the external input signal on UI0 or
UI1 is synchronized with TMCLKIN before being ap-
plied to TMR. The external input signal frequency must
be no higher than 1/2 of the TMCLKIN frequency.
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DS000202-DSP0599