Z8927320VSC Datasheet, PDF (52/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
INSTRUCTION DESCRIPTIONS (Continued)
Inst. Description Synopsis
Operands
Words Cycles Examples
LD
Load
LD<dest>,<src>
A,<hwregs>
1
1
LD A,X
destination
A,<dregs>
1
1
LD A,D0:0
with source
A,<pregs>
1
1
LD A,P0:1
A,<regind>
1
1
LD A,@P1:1
A,<memind>
1
3
LD A,@D0:0
A,<direct>
1
1
LD A,124
<direct>,A
1
1
LD 124,A
<dregs>,<hwregs>
1
1
LD D0:0,EXT7
<pregs>,<simm>
1
1
LD P1:1,#%FA
<pregs>,<hwregs>
1
1
LD P1:1,EXT1
<regind>,<limm>
1
1
LD@P1:1,#1234
<regind>,<hwregs>
1
1
LD @P1:1+,X
<hwregs>,<pregs>
1
1
LD Y,P0:0
<hwregs>,<dregs>
1
1
LD SR,D0:0
<hwregs>,<limm>
2
2
LD PC,#%1234
<hwregs>,<accind>
1
3
LD X,@A
<hwregs>,<memind>
1
3
LD Y,@D0:0
<hwregs>,<regind>
1
1
LD A,@P0:0–LOOP
<hwregs>,<hwregs>
1
1
LD X,EXT6
Notes:
When <dest> is <hwregs>, <dest> cannot be P.
When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be EXTn if <src> is EXTn,
<dest> cannot be X if <src> is X, <dest> cannot be SR if <src> is SR.
When <src> is <accind> <dest> cannot be A.
MLD Multiply
MLD <src1>,<src2> <hwregs>,<regind>
1
1
MLD A,@P0:0+LOOP
[,<bank switch>] <hwregs>,<regind>,
1
1
MLD A,@P1:0,OFF
<bank switch>
1
1
MLD @P1:1,@P2:0
<regind>,<regind>
1
1
MLD @P0:1,@P1:0,ON
<regind>,<regind>,
<bank switch>
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands
<regind>, the <bank switch> defaults to ON.
MPYA Multiply and MPYA <src1>,<src2> <hwregs>,<regind>
1
1
MPYA A,@P0:0
add
[,<bank switch>] <hwregs>,<regind>,
1
1
MPYA A,@P1:0,OFF
<bank switch>
1
1
MPYA @P1:1,@P2:0
<regind>,<regind>
1
1
MPYA@P0:1,@P1:0,ON
<regind>,<regind>,
<bank switch>
Notes:
If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register.
<hwregs> for src1 cannot be X.
For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank
switch> defaults to ON.
MPYS Multiply and MPYS <src1>,<src2> <hwregs>,<regind>
1
1
MPYS A,@P0:0
subtract
[,<bank switch>] <hwregs>,<regind>,
1
1
MPYS A,@P1:0,OFF
<bank switch>
1
1
MPYS @P1:1,@P2:0
<regind>,<regind>
1
1
MPYS
<regind>,<regind>,
@P0:1,@P1:0,ON
<bank switch>
52
DS000202-DSP0599