Z8927320VSC Datasheet, PDF (30/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
BANK/EXT REGISTER ASSIGNMENTS (Continued)
Interrupt Status/Bank Select RegisterÑEXT7
Following is a description of EXT7. It contains both a Bank
Select Field and Interrupt Status Bits.
Bank Select Field. The four LSBs of EXT7 denote which
bank is selected as the current working bank.
Interrupt Status Bits. These bits can be read to identify
which interrupts are pending. A “1” denotes interrupt pend-
ing, and a “0” denotes no interrupt. This ability to identify in-
terrupts is particularly useful in polled interrupt operation or
when servicing ISR2, which may come from several sources.
Note: Write “1” to a particular status bit to clear that bit. Before
exiting an interrupt service routine, the relevant interrupt
bit(s) should be cleared. To clear a bit efficiently:
• Load the value of EXT7 into a register or memory
location
• Then load that value back into EXT7
Performing these steps clear all of the interrupts that
were pending, but leave the Register Bank Select
unchanged.
Ext 7 Reg
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 20. EXT7 Register
Bank Select
0000 : Bank0
0001 : Bank1
:
:
1111 : Bank15
Interrupt Status Bits
Bit 4 = A/D Finish Interrupt
Bit 5 = SPI Interrupt
Bit 6 = Timer0 Interrupt
Bit 7 = Timer1 Interrupt
Bit 8 = Timer2 Interrupt
Bit 9 = INT0 (H/W) Interrupt
Bit 10 = INT1 (H/W) Interrupt
Bit 11 = INT2 (H/W) Interrupt
Reserved
30
DS000202-DSP0599