Z8927320VSC Datasheet, PDF (24/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
FUNCTIONAL DESCRIPTION
Instruction Timing. Most instructions are executed in one
machine cycle. A multiplication or multiply/accumulate in-
struction requires a single cycle. Long immediate instruc-
tions, and Jump or Call instructions, are executed in two ma-
chine cycles. Specific instruction cycle times are described
in the Instruction Description section.
Multiply/Accumulate. The multiplier can perform a 16-
bit x 16-bit multiply, or multiply/accumulate, in one ma-
chine cycle using the Accumulator and/or both the X and
Y inputs. The multiplier produces a 32-bit result, however,
only the 24 most significant bits are saved for the next in-
struction or accumulation. For operations on very small
numbers where the least significant bits are important, the
data should first be scaled to avoid truncation errors.
XDATA
DDATA
Data Bus Bank Switch. There is a switch that connects the
X Bus to the DDATA Bus that allows both the X and Y reg-
isters to be loaded with the same operand for a one cycle
squaring operation. The switch is also used to read the X
register.
ALU. The ALU features two input ports. One is connected
to the output of the 24-bit Accumulator. The other input se-
lects either the Multiplier Unit Output or the 16-bit DDATA
bus (left-justified with zeros in the eight LSBs). The ALU
performs arithmetic, logic, and shift operations.
DDATA
Multiplier Unit 16
Output
24
16
16
•X Register (16)
Y Register (16)
MULTIPLIER
P Register (24)
16 MSB
MUX
24
24
ALU
24
Shift Unit
24
Multiplier Unit
Output
*Options:
No Shift
3 Bits Right
Accumulator (24)
16 MSB
Figure 17. ALU Block Diagram
Figure 16. Multiplier Block Diagram
All inputs to the multiplier should be fractional two’s-com-
plement, 16-bit binary numbers, which places them in the
range [–1 to 0.9999695]. The result is in 24 bits, so the range
is [–1 to 0.9999999].
If 8000H is loaded into both the X and Y registers, the mul-
tiplication produces an incorrect result. Positive one cannot
be represented in fractional notation, and the multiplier ac-
tually yields the result 8000H x 8000H = 8000H (–1 x –1
= –1). The user should avoid this case to prevent erroneous
results.
A shifter between the P Register and the Multiplier Unit
Output can shift the data by three bits right or no shift.
Hardware Stack. A six-level hardware stack is connected
to the DDATA bus to hold subroutine return addresses or
data. The CALL instruction pushes PC+2 onto the stack,
and the RET instruction pops the contents of the stack to
the PC.
User Inputs and Outputs. The Z893x3 features three
User Inputs, UI0, UI1, and UI2. Pins UI0 and UI1 are con-
nected directly to status register bits S10 and S11, and can
be read, or used as a condition code in any conditional in-
struction. Pins UI0, UI1 and UI2 may also be used to clock
the Counter/Timers. There are two user output bits, UO0
and UO1, which share pins with the timer outputs TMO0
and TMO1 on Port2. When the User Outputs are enabled,
they are the complements of bits S5 and S6 of the Status
Register.
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DS000202-DSP0599