Z8927320VSC Datasheet, PDF (51/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
INSTRUCTION DESCRIPTIONS
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
Inst.
ABS
ADD
AND
CALL
CCF
CIEF
COPF
CP
DEC
INC
JP
Description Synopsis
Operands
Absolute
Value
ABS[<cc>,]<src>
<cc>,A
A
Addition
ADD<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
Bitwise AND AND<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
Subroutine CALL
call
[<cc>,]<address>
<cc>,<direct>
<direct>
Clear C flag CCF
None
Clear IE Flag CIEF
None
Clear OP flag COPF
None
Comparison CP<src1>,<src2>
A,<pregs>
A,<dregs>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<limm>
A,<simm>
Decrement DEC [<cc>,]<dest> <cc>A,
A
Increment
INC [<cc>,] <dest> <cc>,A
A
Jump
JP [<cc>,]<address> <cc>,<direct>
<direct>
Words Cycles Examples
1
1
ABS NC, A
1
1
ABS A
1
1
ADD A,P0:0
1
1
ADD A,D0:0
2
2
ADD A,#%1234
1
3
ADD A,@@P0:0
1
1
ADD A,%F2
1
1
ADD A,@P1:1
1
1
ADD A,X
1
1
ADD A, #%12
1
1
AND A,P2:0
1
1
AND A,D0:1
2
2
AND A,#%1234
1
3
AND A,@@P1:0
1
1
AND A,%2C
1
1
AND A,@P1:2+LOOP
1
1
AND A,EXT3
1
1
AND A, #%12
2
2
CALL Z,sub2
2
2
CALL sub1
1
1
CCF
1
1
CIEF
1
1
COPF
1
1
CP A,P0:0
1
1
CP A,D3:1
1
3
CP A,@@P0:1
1
1
CP A,%FF
1
1
CP A,@P2:1+
1
1
CP A,STACK
2
2
CP A,#%FFCF
1
1
CP A, #%12
1
1
DEC NZ,A
1
1
DEC A
1
1
INC PL,A
1
1
INC A
2
2
JP C,Label
2
2
JP Label
DS000202-DSP0599
51