Z8927320VSC Datasheet, PDF(25/60 Page) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

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Z8927320VSC Datasheet, PDF (25/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

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ZiLOG

Z89223/273/323/373

16-Bit Digital Signal Processors with A/D Converter

Interrupts. The Z893x3 features three user interrupt inputs

which can be programmed to be positive or negative edge-

triggered. There are five interrupts generated by internal pe-

ripherals: the A/D converter, the Serial Peripheral Interface,

and the three Counter/Timers. Internally there are three pri-

ority levels. The internal signals for Interrupt service Re-

quests are denoted ISR0, ISR1, and ISR2, with ISR0 having

the highest priority, and ISR2 the lowest. The user can pro-

gram which interrupt sources are enabled, and which sourc-

es are serviced by the highest, middle, and lowest priority

service routines. An interrupt is serviced at the end of an

instruction execution. Two machine cycles are required to

enter an interrupt instruction sequence. The PC is pushed

onto the stack. The Interrupt Controller fetches the address

of the interrupt service routine from the following locations

in program memory:

Device

Z89223/273/323/373

ISR0

1FFFH

ISR1

1FFEH

ISR2

1FFDH

At the end of the interrupt service routine, a RET instruction

is used to pop the stack into the PC.

The Set-Interrupt-Enable-Flag (SIEF) instruction enables

the interrupts. Interrupts are automatically disabled when

entering an interrupt service routine. Before exiting an in-

terrupt service routine the SIEF instruction can be used to

reenable interrupts.

Registers. In addition to the internal registers for process-

ing, control, and configuration, the Z893x3 offers up to sev-

en user-defined 16-bit external registers, EXT0âEXT6, de-

pending on the Register Bank Select value. The external

ripherals. Selecting banks 0â4 of the EXT Register Assign-

ment allows access to/from three to seven of these addresses

for general-purpose use.

I/O Ports. The Z893X3 DSP family features a user-config-

urable I/O structure. Most of the I/O pins include dual func-

tions. The Counter/Timer, Serial Peripheral Interface, and

External Interrupt Enables determine whether a pin is ded-

icated to peripheral or I/O port use.

Port0. A 16-bit user I/O port. Bits can be configured as in-

put or output or globally as open-drain output. When en-

abled, Port0 consumes the 16 data lines used by the ED bus.

Port0 function and ED bus use can be dynamically alter-

nated by enabling and disabling Port0.

Port1. A multifunctional 8-bit port. Bits can be configured

as input or output or globally as open-drain output. Port1

also supports INT2, CLKOUT, the Serial Peripheral Inter-

face, and User Inputs 0 and 1.

Port2. A multifunctional 8-bit port. Bits can be configured

as input or output or globally as open-drain output. Port2

also supports INT0 and INT1, all three Counter/Timer out-

puts, ED Bus, WAIT, and UI2.

Port3. Port3 is an 8-bit user I/O port with 4 bits of input and

4 bits of output. It is available only on the 80-pin package.

External Register Usage. T h e e x t e r n a l r e g i s t e r s

EXT0âEXT6 are accessed using the External Address Bus

EA2âEA0, the External Data Bus (ED Bus) ED15âED0,

and control signals DS, WAIT, and RD/WR. These provide

a convenient data transfer capability with external periph-

erals. Data transfers can be performed in a single-cycle. An

internal wait state generator is provided to accommodate

slower external peripherals. A single wait state can be im-

plemented through control register Bank15/EXT3. For ad-

ditional wait states, the WAIT pin can be used. The WAIT

pin is monitored only during execution of a read or write

instruction to external peripherals on the ED bus.

Wait-State Generator. An internal Wait-State generator

is provided to accommodate slow external peripherals. A

single Wait-State can be implemented through a control

be held Low. The WAIT pin is monitored only during ex-

ecution of a read or write instruction to external peripherals

(ED bus).

Analog to Digital Converter. The A/D Converter is a 4-

channel, 8-bit half-flash converter. Two external reference

voltages provide a scalable input range. The A/D sample

rate is determined by a prescaler connected to the system

clock. An interrupt is optionally generated at the end of a

conversion. The four input channels can be programmed to

operate on demand, continuously, or upon an event (timer

or interrupt).

Counter/Timers (C/T0 and C/T1). These C/Ts are 16-bit

with 8-bit prescalers. They also offer the option of being

used as PWM generators and include both hardware and

software Watch-Dog capabilities. Both C/Ts are identical

and can be externally or internally clocked. Either C/T can

drive TMO0 or TMO1. Either C/T can drive any of the three

interrupt service requests (ISR0, ISR1, or ISR2).

Counter/Timer (C/T2). This C/T is 16-bits, externally or

internally clocked, and can drive TMO2 and/or any of the

three interrupt service requests (ISR0, ISR1, or ISR2).

Serial Peripheral Interface (SPI). The Serial Peripheral

Interface provides a convenient means of inter-processor

and processor-peripheral communication. It offers the ca-

pability to transmit and receive simultaneously. The SPI is

designed to operate in either master or slave mode.

DS000202-DSP0599

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