Z8927320VSC Datasheet, PDF (2/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
GENERAL DESCRIPTION (Continued)
OTP version of the Z89223/323, is ideal for prototypes and
early production builds.
Throughout this specification, references to the Z893x3 de-
vice apply equally to the Z89223/273/323/373, unless oth-
erwise specified.
ZiLOG
Notes: All signals with an overline are active Low. For
example, in RD/WR, RD is active High and WR is
active Low. For I/O ports, P1.3 denotes Port1 bit 3. Pins
called NC are “No Connection”—they do not connect
any power, grounds, or signals.
Power connections follow conventional descriptions:
Connection
Circuit
Device
Power
V_CC
V_DD
Ground
GND
V_SS
Program
ROM/OTP
8192x16
Data RAM0
256x16
D0:0–3:0
Data RAM1
256x16
D0:1–3:1
Port 0
HALT
RESET
CLKI
CLKO
LPF
V_DD
V_SS
AV_CC
AGND
16
16
16
Program
Control
Unit
16
Bank
Switch
16
8
8
Addr
Gen
Unit0
P0:0
P1:0
P2:0
Addr
Gen
Unit1
P0:1
P1:1
P2:1
8
16
8
DDATA
16
16 MSB
16
Phase
Locked
Loop
X
Y
Multiplier
P
24
16 MSB
Shifter
Stack
24
16
MUX
24
24
ALU
24
Accumulator
24
16 MSB
16-Bit Counter
Timer
16-Bit Counter
Timer, PWM
16-Bit Counter
Timer, PWM
SPI
16-Bit
Peripheral
Interface
16
8-Bit
A/D
Port 1
8-Bit I/O
Port 2
8-Bit I/O
4 Inputs
4 Outputs
Figure 1. Z892X3/3x3 Functional Block Diagram
EA2–EA0
ED15–ED0
DS
WAIT
RD/WR
VAHI
AN0
AN1
AN2
AN3
VALO
P1.0 or INT2
P1.1 or CLKOUT
P1.2 or SDI
P1.3 or SDO
P1.4 or SS
P1.5 or SCLK
P1.6 or UI0
P1.7 or UI1
P2.0 or INT0
P2.1 or INT1
P2.2 or TMO0
P2.3 or TMO1
P2.4 or WAIT
P2.5 or UI2
P2.6 or TMO2
P2.7
P3.7–P3.4
P3.3–P3.0
2
DS000202-DSP0599