Z8927320VSC Datasheet, PDF (48/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
SYSTEM CLOCK GENERATOR (Continued)
mined by the PLL Divisor value in the MSB of the Clock
Control Register, Bank15/EXT5:
VCO Frequency = 4 x PLL Divisor x PLL In Frequency.
The PLL Divisor value should be between 1 and156 to ob-
tain a VCO Frequency between 128 kHz and 20 MHz from
a 32-kHz input.
There are four options for PLL Out: VCO Out, VCO Out
divided by 2, VCO Out divided by four, or twice the crystal
frequency. This selection is determined by the PLL Out Se-
lect bits in the Clock Control Register.
Note: The PLL is designed and tested to operate with an input
frequency of approximately 32 kHz. It is possible to
drive the input with a crystal or user-generated clock at
some other frequency, but the results are not guaranteed.
Sleep Modes
The Z893x3 supports various Clock Modes to minimize de-
vice power consumption. The lowest power mode is Deep
Sleep in which the System Clock is stopped, and the VCO
and XTAL Oscillator are both turned off.
ZiLOG
Table 23. Standard Clock Mode Summary
Mode
Power-up/Reset
(default)
PLL Clock
Crystal Oscillator
Direct
External Clock Direct
Deep Sleep
(lowest power)
Stop
Sys
CLKI XTAL Stop Clk
Src Osc. VCO Sel
XTAL, 0
0
0
User
XTAL 0
0
1
XTAL 0
1
0
User 1
1
0
XTAL, 1
1
1
User
Wake-Up From Sleep Modes
The Wake-up Trigger Source is specified by bits 5 and 6
of the Clock Control Register. The polarity of the Wake-
up signal is defined by bit 7. Wake-up occurs when the
wake-up signal is toggled to the specified wake-up polarity.
Wake-up resumes operation starting from the reset vector
address in the same way the chip responds to an external
RESET.
Bank 15/Ext 5 Reg
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
STOP_OSC
0 : Oscillator Running
1 : Stop Oscillator
STOP_VCO
0 : VCO Running
1 : Stop VCO
BYPASS_PLL
0 : Clock Source is Oscillator
1 : Clock Source is VCO
DSP (System) Clock Source
00 : VCO Clock
01 : VCO Clock Divided by 2
10 : VCO Clock Divided by 4
11 : Twice the Crystal Frequency
Recovery Source
00 : POR (Power-On Reset) or
Port 2, Bit 0 (INT0)
01 : POR or Port 1, Bit 4 (SS)
10 : POR or Port 1, Bit 6 (UI0)
11 : POR or Port 2, Bit 0 or
Port 1, Bit 4 or Port 1, Bit 6
STOP Recovery Level
0 : Low (Default setting after reset)
1 : High
Programmable PLL Divider Register
System Clock = Bits 15Ð8 x 4 x Crystal Frequency (32.768 kHz)
Figure 43. System Clock Control Register
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DS000202-DSP0599