Z8927320VSC Datasheet, PDF (27/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
REGISTERS
Both external and internal registers are accessed in one ma-
chine cycle. The external registers are used to access the on-
chip peripherals when they are enabled.
The internal registers of the Z893X3 are defined below:
Register
X
Y
P
A
Pn:b
PC
SR
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
Register Definition
Multiplier X Input, 16-bits
Multiplier Y Input, 16-bits
Multiplier Output, 24-bits
Accumulator, 24-bits
Six Data RAM Pointers, 8-bits each
Program Counter, 16-bits
Status Register, 16-bits
depends on Bank Select #, 16-bits
depends on Bank Select #, 16-bits
depends on Bank Select #, 16-bits
depends on Bank Select #, 16-bits
depends on Bank Select #, 16-bits
depends on Bank Select #, 16-bits
depends on Bank Select #, 16-bits
Interrupt Status/Bank Select, 16-bits
only be read by software. S9–S0 control hardware opera-
tions and can be written by software.
Table 11. Status Register Bit Functions
SR Bit
Function
Read/Write
S15 (N)
S14 (OV)
S13 (Z)
S12 (C)
S11 (UI1)
S10 (UI0)
S9 (SH3)
S8 (OP)
S7 (IE)
S6 (UO1)
S5 (UO0)
S4–S3
S2–S0 (RPL)
ALU Negative
RO
ALU Overflow
RO
ALU Zero
RO
Carry
RO
User Input 1
RO
User Input 0
RO
MPY Output
R/W
Arithmetically Shifted
Right by Three Bits
Overflow Protection
R/W
Interrupt Enable
R/W
User Output 1
R/W
User Output 0
R/W
“Short Form Direct” bits R/W
RAM Pointer Loop Size R/W
X and Y are two 16-bit input registers for the multiplier.
These registers can be utilized as temporary registers when
the multiplier is not being used.
P holds the result of multiplications and is read-only.
A is a 24-bit Accumulator. The output of the ALU is sent
to this register. When 16-bit data is transferred into this reg-
ister, it is placed into the 16 MSBs and the least significant
eight bits are set to zero. Only the upper 16 bits are trans-
ferred to the destination register when the Accumulator is
selected as a source register in transfer instructions.
Pn:b are the pointer registers for accessing data RAM where
n = 0, 1, or 2, and b = 0 or 1. They can be directly read or
written. They point to locations in data RAM.
PC is the Program Counter. Any instruction which may
modify this register requires two clock cycles.
SR is the status register. It contains the ALU status and pro-
cessor control bits. The status register can always be read
in its entirety. S15–S10 are set/reset by hardware and can
Note: RO = read only, RW = read/write. The status register can
always be read in its entirety.
S15–S12 are set/reset by the ALU after an operation.
S11–S10 are set/reset by the user input pins.
If S9 is set and a multiply/shift option is used, the shifter
shifts the result three bits right. This feature allows the data
to be scaled and prevents overflows.
If S8 is set, the hardware clamps at maximum positive or
negative values instead of overflowing.
S7 enables interrupts.
S6–S5 are User Outputs. The complement of the value in
the Status Register appears on bits 2 and 3 of Port2 if the
User Outputs are enabled by writing a 1 to Bit 15 of Bank
15–EXT3, and Counter/Timer 0 and 1 are disabled.
S4–S3 are the two MSBs in the “short form direct” mode
of addressing.
S2–S0 define the RAM pointer loop size as indicated in Ta-
ble 12.
DS000202-DSP0599
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