Z8927320VSC Datasheet, PDF (39/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

ZiLOG
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
Bank13/EXT0 (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
CSEL0
CSEL1
(Reserved)
SCAN
QUAD
DIV0
DIV1
DIV2
Figure 29. ADCTL Register (LSB)
Table 18. A/D Prescaler Values (Bits 7, 6, 5)
DIV2
0
0
0
0
1
1
1
1
DIV1
0
0
1
1
0
0
1
1
DIV0
0
1
0
1
0
1
0
1
A/D Prescaler
(Crystal divided by)
8
16
24
32
40
48
56
64
Table 19. Operating Modes (Bits 4, 3)
QUAD
0
0
1
1
SCAN Option
0 Convert selected channel 4 times,
then stop
1 Convert selected channel,
then stop.
0 Convert 4 channels,
then stop.
1 Convert 4 channels
continuously.
Table 20. Channel Select (Bits 1, 0)
CSEL1
0
0
1
1
CSEL0
0
1
0
1
Channel
AN0
AN1
AN2
AN3
Bank13/EXT0 (MSB)
D15 D14 D13 D12 D11 D10 D9 D8
ADST0
ADST1
ADIE
ADIT
ADCINT
(Reserved)
ADE
Figure 30. ADCTL Register (MSB)
ADE (Bit 15). A “0” disables any A/D conversions or ac-
cessing any A/D registers, except writing to the ADE bit.
A “1” enables all A/D accesses.
Reserved (Bits 14, 13). Reserved for future use.
ADCINT (Bit 12). The A/D interrupt bit is read-only. The
ADCINT will reset every time this register is written.
ADIT (Bit 11). Selects when to set the A/D interrupt if in-
terrupts are enabled (ADIE=1). A value of “0” sets the in-
terrupt after the first A/D conversion is complete. A value
of “1” sets the interrupt after the fourth A/D conversion is
complete.
ADIE (Bit 10). A/D Interrupt Enable. A value of “0” dis-
ables the A/D Interrupt. A value of “1” enables the A/D In-
terrupt.
ADST1
0
0
1
1
Table 21. START (Bits 9, 8)
ADST0
0
1
0
1
Option
Conversion starts when this
register is written.
Conversion starts on INT1 per
Interrupt Allocation Register
Conversion starts on C/T2
time-out.
Conversion starts on C/T0
time-out.
There are four A/D result registers. See the EXT Register
Assignments for their location in the different banks.
DS000202-DSP0599
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