Z8927320VSC Datasheet, PDF (44/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

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16-Bit Digital Signal Processors with A/D Converter
GENERAL-PURPOSE COUNTER/TIMER (C/T2) (Continued)
ZiLOG
Bank 15/EXT2
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Port2 I/O Directions
0 = Input (default)
1 = Output
Port3
0 = Disabled (default)
1 = Enabled
INT0
0 = Disabled (default)
1 = Enabled
Port2 Outputs
0 = Push-Pull (default)
1 = Open-Drain
Counter/Timer2
0 = Disabled (default)
1 = Enabled
Counter/Timer2 Operation
0 = Stopped (default)
1 = Counting
If D15 = 0, Counter/Timer2 Clock defined by
0 = System Clock/2 (default)
1 = UI2
If D15 = 1, Counter/Timer2 Sleep Mode Wake-Up
0 = Disabled (default)
1 = Enabled
TMO2
0 = Disabled (default)
1 = Enabled
Counter/Timer2 Clock
0 = Defined by D13 (default)
1 = CLKI
Figure 38. Counter/Timer2 Control Register
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DS000202-DSP0599