Z8927320VSC Datasheet, PDF (46/60 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER

Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
SERIAL PERIPHERAL INTERFACE (Continued)
Slave Mode Operation
SS must be asserted to enable a data transfer. Incoming data
on the SDI pin is shifted into the SPI Shift Register one data
bit per SCLK cycle. When a byte of data is received, the
SPI Shift Register contents are automatically copied into
RxBUF. The Receive Byte Available flag is set, and if en-
abled, an SPI interrupt is generated. The next byte of data
may be received at this time. The current byte in RxBUF
must be read before the next byte’s reception is complete,
or the Receive Byte Overrun flag will set, and the data in
RxBUF will be overwritten. The Receive Byte Available
flag is reset when RxBUF is read.
Unless the SPI output, SDO, is disabled, for every bit that
is transferred into the slave through the SDI pin, a bit is
transferred out through the SDO pin on the opposite clock
edge. During slave operation, SCLK is an input.
Note: Slave Mode is not available on the 44-pin package.
C/T0
System
Clock
(from PLL Block)
SPI Clock
SPI
Counter
Interrupt
SPI Shift Register
SPI Receive Buffer (RxBuf)
SCLK/P1.5
SPI•
I/O
SDO/P1.3
SDI/P1.2
SS/P1.4
SPI Control (SCON)
INT
Figure 41. SPI Block Diagram
46
DS000202-DSP0599