XC3S50A-4TQG144C Datasheet, PDF (94/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
FG320: 320-ball Fine-pitch Ball Grid Array
The 320-ball fine-pitch ball grid array package, FG320,
supports two Spartan-3A FPGAs, the XC3S200A and the
XC3S400A, as shown in Table 77 and Figure 23.
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
Table 77 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The shaded rows indicate pinout differences between the
XC3S200A and the XC3S400A FPGAs. The XC3S200A
has three unconnected balls, indicated as N.C. (No
Connection) in Table 77 and with the black diamond
character (‹) in Table 77 and Figure 23.
All other balls have nearly identical functionality on all three
devices. Table 80 summarizes the Spartan-3A FPGA
footprint migration differences for the FG320 package.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 77: Spartan-3A FG320 Pinout
Bank
Pin Name
FG320
Ball
0
IO_L01N_0
C15
0
IO_L01P_0
C16
0
IO_L02N_0
A16
0
IO_L02P_0/VREF_0
B16
0
IO_L03N_0
A14
0
IO_L03P_0
A15
0
IO_L04N_0
C14
0
IO_L04P_0
B15
0
IO_L05N_0
D12
0
IO_L05P_0
C13
0
IO_L06N_0/VREF_0
A13
0
IO_L06P_0
B13
0
IO_L07N_0
B12
0
IO_L07P_0
C12
0
IO_L08N_0
F11
0
IO_L08P_0
E11
0
IO_L09N_0
A11
Type
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
Table 77: Spartan-3A FG320 Pinout(Continued)
Bank
Pin Name
FG320
Ball
Type
0
IO_L09P_0
B11
I/O
0
IO_L10N_0
D10
I/O
0
IO_L10P_0
C11
I/O
0
IO_L11N_0/GCLK5
C9
GCLK
0
IO_L11P_0/GCLK4
B10 GCLK
0
IO_L12N_0/GCLK7
B9
GCLK
0
IO_L12P_0/GCLK6
A10 GCLK
0
IO_L13N_0/GCLK9
B7
GCLK
0
IO_L13P_0/GCLK8
A8
GCLK
0
IO_L14N_0/GCLK11
C8
GCLK
0
IO_L14P_0/GCLK10
B8
GCLK
0
IO_L15N_0
C7
I/O
0
IO_L15P_0
D8
I/O
0
IO_L16N_0
E9
I/O
0
IO_L16P_0
D9
I/O
0
IO_L17N_0
B6
I/O
0
IO_L17P_0
A6
I/O
0
IO_L18N_0/VREF_0
A4
VREF
0
IO_L18P_0
A5
I/O
0
IO_L19N_0
E7
I/O
0
IO_L19P_0
F8
I/O
0
IO_L20N_0
D6
I/O
0
IO_L20P_0
C6
I/O
0
IO_L21N_0
A3
I/O
0
IO_L21P_0
B4
I/O
0
IO_L22N_0
D5
I/O
0
IO_L22P_0
C5
I/O
0
IO_L23N_0
A2
I/O
0
IO_L23P_0
B3
I/O
0
IO_L24N_0/PUDC_B
E5
DUAL
0
IO_L24P_0/VREF_0
E6
VREF
0
IP_0
D13 INPUT
0
IP_0
D14 INPUT
0
IP_0
E12 INPUT
0
XC3S400A: IP_0
XC3S200A: N.C. (◆)
E13 INPUT
0
IP_0
F7
INPUT
0
IP_0
F9
INPUT
0
IP_0
F10 INPUT
94
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DS529-4 (v2.0) August 19, 2010