XC3S50A-4TQG144C Datasheet, PDF (75/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
TQ144: 144-lead Thin Quad Flat Package
The XC3S50A is available in the 144-lead thin quad flat
package, TQ144.
Table 66 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 66: Spartan-3A TQ144 Pinout
Bank
Pin Name
0
IO_0
0
IO_L01N_0
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0/VREF_0
0
IO_L03N_0
0
IO_L03P_0
0
IO_L04N_0
0
IO_L04P_0
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0/GCLK5
0
IO_L06P_0/GCLK4
0
IO_L07N_0/GCLK7
0
IO_L07P_0/GCLK6
0
IO_L08N_0/GCLK9
0
IO_L08P_0/GCLK8
0
IO_L09N_0/GCLK11
0
IO_L09P_0/GCLK10
0
IO_L10N_0
0
IO_L10P_0
0
IO_L11N_0
0
IO_L11P_0
0
IO_L12N_0/PUDC_B
0
IO_L12P_0/VREF_0
0
IP_0
Pin
P142
P111
P110
P113
P112
P117
P115
P116
P114
P121
P120
P126
P124
P127
P125
P131
P129
P132
P130
P135
P134
P139
P138
P143
P141
P140
Type
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
I/O
I/O
I/O
DUAL
VREF
INPUT
Table 66: Spartan-3A TQ144 Pinout(Continued)
Bank
Pin Name
Pin
Type
0
IP_0/VREF_0
P123 VREF
0
VCCO_0
P119 VCCO
0
VCCO_0
P136 VCCO
1
IO_1
P79
I/O
1
IO_L01N_1/LDC2
P78 DUAL
1
IO_L01P_1/HDC
P76 DUAL
1
IO_L02N_1/LDC0
P77 DUAL
1
IO_L02P_1/LDC1
P75 DUAL
1
IO_L03N_1
P84
I/O
1
IO_L03P_1
P82
I/O
1
IO_L04N_1/RHCLK1
P85 RHCLK
1
IO_L04P_1/RHCLK0
P83 RHCLK
1
IO_L05N_1/TRDY1/RHCLK3
P88 RHCLK
1
IO_L05P_1/RHCLK2
P87 RHCLK
1
IO_L06N_1/RHCLK5
P92 RHCLK
1
IO_L06P_1/RHCLK4
P90 RHCLK
1
IO_L07N_1/RHCLK7
P93 RHCLK
1
IO_L07P_1/IRDY1/RHCLK6
P91 RHCLK
1
IO_L08N_1
P98
I/O
1
IO_L08P_1
P96
I/O
1
IO_L09N_1
P101
I/O
1
IO_L09P_1
P99
I/O
1
IO_L10N_1
P104
I/O
1
IO_L10P_1
P102
I/O
1
IO_L11N_1
P105
I/O
1
IO_L11P_1
P103
I/O
1
IP_1/VREF_1
P80 VREF
1
IP_1/VREF_1
P97 VREF
1
VCCO_1
P86 VCCO
1
VCCO_1
P95 VCCO
2
IO_2/MOSI/CSI_B
P62 DUAL
2
IO_L01N_2/M0
P38 DUAL
2
IO_L01P_2/M1
P37 DUAL
2
IO_L02N_2/CSO_B
P41 DUAL
2
IO_L02P_2/M2
P39 DUAL
2
IO_L03N_2/VS1
P44 DUAL
2
IO_L03P_2/RDWR_B
P42 DUAL
2
IO_L04N_2/VS0
P45 DUAL
2
IO_L04P_2/VS2
P43 DUAL
2
IO_L05N_2/D7
P48 DUAL
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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