XC3S50A-4TQG144C Datasheet, PDF (116/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
User I/Os by Bank
Table 84 and Table 85 indicate how the user-I/O pins are
distributed between the four I/O banks on the FG484
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 84: User I/Os Per Bank for the XC3S700A in the FG484 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
92
58
17
1
8
Right
1
94
33
15
30
8
Bottom
2
92
43
11
21
9
Left
3
94
61
17
0
8
TOTAL
372
195
60
52
33
CLK
8
8
8
8
32
Table 85: User I/Os Per Bank for the XC3S1400A in the FG484 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
92
58
17
1
8
Right
1
94
33
15
30
8
Bottom
2
95
43
13
21
10
Left
3
94
61
17
0
8
TOTAL
375
195
62
52
34
Footprint Migration Differences
Table 86 summarizes any footprint and functionality
differences between the XC3S700A and the XC3S1400A
FPGAs that might affect easy migration between devices
available in the FG484 package. There are three such balls.
All other pins not listed in Table 86 unconditionally migrate
between Spartan-3A devices available in the FG484
package.
The arrows indicate the direction for easy migration.
Table 86: FG484 Footprint Migration Differences
Pin Bank XC3S700A Migration XC3S1400A
T8
2 N.C.
Æ
INPUT/VREF
U7
2 N.C.
Æ
INPUT
U16
2 N.C.
Æ
INPUT
DIFFERENCES
3
Legend:
Æ
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
CLK
8
8
8
8
32
116
www.xilinx.com
DS529-4 (v2.0) August 19, 2010