XC3S50A-4TQG144C Datasheet, PDF (25/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Symbol
T_IOPICKD
Description
Conditions
Time from the setup of data at the LVCMOS25⁽²⁾
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
Hold Times
T_IOICKP
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
LVCMOS25⁽³⁾
T_IOICKPD
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
LVCMOS25⁽³⁾
IFD_
DELAY_
VALUE
Device
1 XC3S700A
2
3
4
5
6
7
8
1 XC3S1400A
2
3
4
5
6
7
8
0 XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
1 XC3S50A
2
3
4
5
6
7
8
1 XC3S200A
2
3
4
5
6
7
8
Speed Grade
-5
-4
Min
Min
1.82
1.95
2.62
2.83
3.32
3.72
3.83
4.31
3.69
4.14
4.60
5.19
5.39
6.10
5.92
6.73
1.79
2.17
2.55
2.92
3.38
3.76
3.75
4.32
3.81
4.19
4.39
5.09
5.16
5.98
5.69
6.57
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–0.66 –0.64 ns
–0.85 –0.65 ns
–0.42 –0.42 ns
–0.81 –0.67 ns
–0.71 –0.71 ns
–0.88 –0.88 ns
–1.33 –1.33 ns
–2.05 –2.05 ns
–2.43 –2.43 ns
–2.34 –2.34 ns
–2.81 –2.81 ns
–3.03 –3.03 ns
–3.83 –3.57 ns
–1.51 –1.51 ns
–2.09 –2.09 ns
–2.40 –2.40 ns
–2.68 –2.68 ns
–2.56 –2.56 ns
–2.99 –2.99 ns
–3.29 –3.29 ns
–3.61 –3.61 ns
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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