XC3S50A-4TQG144C Datasheet, PDF (54/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
V_CCINT
1.2V
(Supply)
1.0V
V_CCAUX
(Supply)
2.0V
2.5V
or
3.3V
V_CCO Bank 2
(Supply)
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Output)
2.0V
T_POR
T_PROG
T_PL
T_ICCK
2.5V
or
3.3V
DS529-3_01_052708
Notes:
1. The V_CCINT, V_CCAUX, and V_CCO supplies can be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 11: Waveforms for Power-On and the Beginning of Configuration
Table 45: Power-On Timing and the Beginning of Configuration
Symbol
T_POR(2)
T_PROG
T_PL(2)
T_INIT
T_ICCK(3)
Description
Device
The time from the application of V_CCINT, V_CCAUX, and V_CCO All
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
All
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Minimum Low pulse width on INIT_B output
All
The time from the rising edge of the INIT_B pin to the
All
generation of the configuration clock signal at the CCLK
output pin
All Speed Grades
Min
Max
–
18
0.5
-
–
0.5
–
0.5
–
1
–
2
–
2
250
–
0.5
4
Units
ms
µs
ms
ms
ms
ms
ms
ns
µs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all V_CCINT, V_CCO,
and V_CCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, and BPI modes.
4. For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide.
54
www.xilinx.com
DS529-3 (v2.0) August 19, 2010