XC3S50A-4TQG144C Datasheet, PDF (24/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
Setup Times
T_IOPICK
Time from the setup of data at the LVCMOS25⁽²⁾
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
T_IOPICKD
Time from the setup of data at the LVCMOS25⁽²⁾
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
IFD_
DELAY_
VALUE
Device
0 XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
1 XC3S50A
2
3
4
5
6
7
8
1 XC3S200A
2
3
4
5
6
7
8
1 XC3S400A
2
3
4
5
6
7
8
Speed Grade
-5
-4
Min
Min
Units
1.56
1.58
ns
1.71
1.81
ns
1.30
1.51
ns
1.34
1.51
ns
1.36
1.74
ns
2.16
2.18
ns
3.10
3.12
ns
3.51
3.76
ns
4.04
4.32
ns
3.88
4.24
ns
4.72
5.09
ns
5.47
5.94
ns
5.97
6.52
ns
2.05
2.20
ns
2.72
2.93
ns
3.38
3.78
ns
3.88
4.37
ns
3.69
4.20
ns
4.56
5.23
ns
5.34
6.11
ns
5.85
6.71
ns
1.79
2.02
ns
2.43
2.67
ns
3.02
3.43
ns
3.49
3.96
ns
3.41
3.95
ns
4.20
4.81
ns
4.96
5.66
ns
5.44
6.19
ns
24
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DS529-3 (v2.0) August 19, 2010