XC3S50A-4TQG144C Datasheet, PDF(117/132 Page) Xilinx, Inc – Spartan-3A FPGA Family

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XC3S50A-4TQG144C Datasheet, PDF (117/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

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FG484 Footprint

Left Half of FG484

Package (Top View)

I/O: Unrestricted,

195 general-purpose user I/O

60-

62

INPUT: Unrestricted,

general-purpose input pin

51

DUAL: Configuration pins,

then possible user I/O

33-

34

VREF: User I/O or input

voltage reference for bank

CLK: User I/O, input, or

32 clock buffer input

SUSPEND: Dedicated

2

SUSPEND and

dual-purpose AWAKE

Power Management pins

2

CONFIG: Dedicated

configuration pins

JTAG: Dedicated JTAG port

4 pins

GND: Ground

53

VCCO: Output voltage

24 supply for bank

VCCINT: Internal core

15 supply voltage (+1.2V)

VCCAUX: Auxiliary supply

10 voltage

3

â

N.C.: Not connected

(XC3S700A only)

DS529-4 (v2.0) August 19, 2010

Pinout Descriptions

Bank 0

1

2

3

4

5

6

7

8

9

10 11

I/O

A GND L36N_0

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

L18N_0

PUDC_B L33P_0 L31P_0 L28N_0 L26N_0 L26P_0 L22N_0 L22P_0 L21P_0 GCLK7

B

I/O

L02P_3

I/O

L36P_0

VREF_0

I/O

L33N_0

I/O VCCO_0

L31N_0

I/O

L28P_0

GND

I/O

L25P_0

I/O

L24P_0

VCCO_0

I/O

L19P_0

GCLK8

C I/O

I/O

GND

L01P_3 L02N_3

I/O

L32P_0

I/O

L29P_0

I/O

L27N_0

I/O

L25N_0

I/O

L24N_0

VREF_0

I/O

L21N_0

I/O

L19N_0

GCLK9

D I/O

I/O

I/O

L06P_3 L01N_3 L03P_3

TMS

I/O

I/O

I/O

I/O

GND

L32N_0 L29N_0 L27P_0 L30N_0

I/O

L23P_0

I/O

L20P_0

GCLK10

E

I/O VCCO_3 I/O

L06N_3

L07N_3

I/O VCCAUX I/O

L03N_3

L35N_0

I/O

L34P_0

INPUT

I/O

L30P_0

I/O

L23N_0

I/O

L20N_0

GCLK11

F I/O

I/O

I/O

I/O

TDI

L12N_3 L12P_3 L08P_3 L07P_3

GND

I/O

I/O VCCO_0 INPUT GND

L35P_0 L34N_0

G I/O

GND

I/O

I/O

I/O

I/O INPUT INPUT INPUT INPUT INPUT

L13N_3

L13P_3 L08N_3 L05N_3 L05P_3

VREF_0

H

I/O

L16N_3

I/O

L16P_3

I/O

L14N_3

I/O

L14P_3

I/O

L09P_3

I/O

L09N_3

INPUT

L04N_3

VREF_3

INPUT

L04P_3

INPUT

VREF_0

INPUT

VCCAUX

J

I/O

L17N_3 VCCO_3

VREF_3

I/O

L17P_3

GND

I/O VCCO_3 INPUT INPUT GND VCCINT GND

L10N_3

L11P_3 VREF_3

I/O

K L22P_3

LHCLK2

I/O

L20N_3

I/O

L20P_3

I/O

L18N_3

I/O

L18P_3

I/O

L10P_3

INPUT

L15P_3

INPUT VCCINT

L11N_3

GND

VCCINT

I/O

L

L22N_3

IRDY2

LHCLK3

GND

I/O

I/O

L21N_3 VCCAUX L21P_3

LHCLK1

LHCLK0

GND

INPUT INPUT

L19P_3

L15N_3

VREF_3

GND VCCINT GND

I/O

M L24P_3

LHCLK4

I/O

L24N_3

LHCLK5

I/O

L25P_3

TRDY2

LHCLK6

I/O

L25N_3

LHCLK7

I/O

L30P_3

INPUT

L23N_3

INPUT

L23P_3

INPUT VCCINT

L19N_3

GND

VCCINT

I/O

N L26P_3 VCCO_3

I/O

VREF_3

L26N_3

I/O

L30N_3

INPUT

L31N_3

INPUT

L31P_3

INPUT

L35P_3

INPUT

L27P_3

INPUT VCCINT

L27N_3

GND

P I/O

I/O

I/O

GND

I/O VCCO_3 INPUT INPUT GND

L28P_3 L28N_3 L29P_3

L29N_3

L39P_3 L35N_3

GND VCCAUX

R I/O

I/O

I/O

I/O

I/O INPUT INPUT INPUT INPUT INPUT INPUT

L32P_3 L32N_3 L33P_3 L33N_3 L34P_3 VREF_3 L46P_3 L39N_3

I/O

T L36P_3

VREF_3

U I/O

L37P_3

GND

I/O

L37N_3

I/O

L36N_3

I/O

L41P_3

I/O

L34N_3

I/O

L41N_3

I/O

L40P_3

I/O

L40N_3

INPUT

L46N_3

VREF_3

INPUT

VREF_2

INPUT

VREF_2

â

INPUT

INPUT

VREF_2

INPUT

VREF_2

GND

INPUT

I/O

â

INPUT VCCO_2 INPUT L17P_2

GCLK12

V

I/O VCCO_3 I/O

L38P_3

L38N_3

I/O

L43P_3

VCCAUX

I/O

L01P_2

M1

INPUT

INPUT I/O

I/O

VREF_2

L09P_2

RDWR_B

L13P_2

I/O

L17N_2

GCLK13

W I/O

L42P_3

I/O

L42N_3

I/O

L43N_3

I/O

L02P_2

M2

I/O

L01N_2

M0

I/O

L05P_2

I/O

L07P_2

I/O

L11P_2

VS1

I/O

L09N_2

VS2

GND VCCAUX

Y I/O

I/O

L44P_3 L44N_3

GND

I/O

L02N_2

CSO_B

I/O

L05N_2

I/O

L07N_2

I/O

L10P_2

I/O

L11N_2

VS0

I/O

L14P_2

D7

I/O

L13N_2

I/O

L16P_2

D5

A I/O

I/O

I/O

I/O VCCO_2 I/O

A L45P_3 L45N_3 L03N_2 L04N_2

L08P_2

GND

I/O VCCO_2 I/O

L12P_2

L15P_2

GND

A

B

GND

I/O

L03P_2

I/O

L04P_2

I/O

L06P_2

I/O

L06N_2

I/O

L08N_2

I/O

L10N_2

I/O

L12N_2

I/O

L14N_2

D6

I/O

L15N_2

I/O

L16N_2

D4

Bank 2

Figure 25: FG484 Package Footprint (Top View)

DS529-4 01 101106

www.xilinx.com

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