XC3S50A-4TQG144C Datasheet, PDF (72/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
User I/Os by Bank
Table 64 indicates how the 68 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.
Table 64: User I/Os Per Bank for the XC3S50A and XC3S200A in the VQ100 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
15
3
1
1
3
Right
1
13
6
0
0
1
Bottom
2
26
2
0
19
1
Left
3
14
6
1
0
1
TOTAL
68
17
2
20
6
CLK
7
6
4
6
23
Footprint Migration Differences
The XC3S50A and XC3S200 have common VQ100 pinouts
except for some differences in alignment of differential I/O
pairs.
Differential I/O Alignment Differences
Some differential I/O pairs in the VQ100 on the XC3S50A
FPGA are aligned differently than the corresponding pairs
on the XC3S200A FPGAs, as shown in Table 65. All the
mismatched pairs are in I/O Bank 2. These differences are
indicated with the black diamond character (‹) in the
footprint diagrams Figure 17 and Figure 18.
Table 65: Differential I/O Differences in VQ100
VQ100 Pin Bank
XC3S50A
XC3S200A
P29
IIO_L04P_2/VS2 IO_L03N_2/VS2
P30
IO_L03N_2/VS1 IO_L04P_2/VS1
P33
IO_L06P_2
IO_L05N_2
P34
2 _{IO_L05N_2/D7}
IO_L06P_2/D7
P51
IO_L11N_2/D0/DIN/ IO_L12P_2/D0/DIN/
MISO
MISO
P52
IO_L12P_2/D1
IO_L11N_2/D1
72
www.xilinx.com
DS529-4 (v2.0) August 19, 2010