XC3S50A-4TQG144C Datasheet, PDF (32/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Output Propagation Times
Table 24: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
Clock-to-Output Times
T_IOCKP When reading from the Output Flip-Flop (OFF), LVCMOS25⁽²⁾, 12 mA output All
the time from the active transition at the OCLK drive, Fast slew rate
input to data appearing at the Output pin
Propagation Times
T_IOOP The time it takes for data to travel from the IOB’s LVCMOS25⁽²⁾, 12 mA output All
O input to the Output pin
drive, Fast slew rate
Set/Reset Times
T_IOSRP
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
LVCMOS25⁽²⁾, 12 mA output All
drive, Fast slew rate
T_IOGSRQ
Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Speed Grade
-5
-4
Max
Max
2.87
3.13
2.78
2.91
3.63
3.89
8.62
9.65
Units
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
Three-State Output Propagation Times
Table 25: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Synchronous Output Enable/Disable Times
T_IOCKHZ
T_IOCKON(2)
Time from the active transition at the OTCLK input of LVCMOS25, 12 mA
the Three-state Flip-Flop (TFF) to when the Output output drive, Fast slew
pin enters the high-impedance state
rate
Time from the active transition at TFF’s OTCLK input
to when the Output pin drives valid data
Asynchronous Output Enable/Disable Times
T_GTS
Time from asserting the Global Three State (GTS)
input on the STARTUP_SPARTAN3A primitive to
when the Output pin enters the high-impedance
state
LVCMOS25, 12 mA
output drive, Fast slew
rate
Set/Reset Times
T_IOSRHZ
T_IOSRON(2)
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to when
the Output pin drives valid data
LVCMOS25, 12 mA
output drive, Fast slew
rate
Device
All
All
All
All
All
Speed Grade
-5
-4
Max Max
Units
0.63 0.76
ns
2.80 3.06
ns
9.47 10.36 ns
1.61 1.86
ns
3.57 3.82
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
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DS529-3 (v2.0) August 19, 2010