XC3S50A-4TQG144C Datasheet, PDF (4/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Introduction and Ordering Information
Architectural Overview
The Spartan-3A family architecture consists of five
fundamental programmable functional elements:
• Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
• Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus 3-state
operation. Supports a variety of signal standards,
including several high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
• Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
• Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
• Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50A, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50A has DCMs only at the
top, while the XC3S700A and XC3S1400A add two DCMs in
the middle of the two columns of block RAM and multipliers.
The Spartan-3A family features a rich network of routing that
interconnect all five functional elements, transmitting signals
among them. Each functional element has an associated
switch matrix that permits multiple connections to the
routing.
IOBs
CLB
DCM
IOBs
DCM
CLBs
DCM
IOBs
DS312-1_01_032606
Notes:
1. The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3A FPGA Architecture
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DS529-1 (v2.0) August 19, 2010