XC3S50A-4TQG144C Datasheet, PDF (14/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins⁽¹⁾
Symbol
Description
I_L(2) Leakage current at User I/O,
input-only, dual-purpose, and
dedicated pins, FPGA powered
Test Conditions
Driver is in a high-impedance state,
V_IN = 0V or V_CCO max, sample-tested
Min Typ Max
–10
–
+10
I_HS
I_RPU(3)
R_PU(3)
I_RPD(3)
R_PD(3)
I_REF
C_IN
R_DT
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
Current through pull-up resistor
at User I/O, dual-purpose,
input-only, and dedicated pins.
Dedicated pins are powered by
V_CCAUX.
Equivalent pull-up resistor value
at User I/O, dual-purpose,
input-only, and dedicated pins
(based on I_RPU per Note 3)
Current through pull-down
resistor at User I/O,
dual-purpose, input-only, and
dedicated pins. Dedicated pins
are powered by V_CCAUX.
Equivalent pull-down resistor
value at User I/O, dual-purpose,
input-only, and dedicated pins
(based on I_RPD per Note 3)
V_REF current per pin
Input capacitance
V_IN = GND
V_IN = GND
V_IN = V_CCO
V_CCO or V_CCAUX =
3.0V to 3.6V
V_CCO or V_CCAUX =
2.3V to 2.7V
V_CCO = 1.7V to 1.9V
V_CCO = 1.4V to 1.6V
V_CCO = 1.14V to 1.26V
V_CCO = 3.0V to 3.6V
V_CCO = 2.3V to 2.7V
V_CCO = 1.7V to 1.9V
V_CCO = 1.4V to 1.6V
V_CCO = 1.14V to 1.26V
V_CCAUX = 3.0V to 3.6V
V_CCAUX = 2.25V to 2.75V
V_CCAUX = 3.0V to 3.6V
V_IN = 3.0V to 3.6V
V_IN = 2.3V to 2.7V
V_IN = 1.7V to 1.9V
V_IN = 1.4V to 1.6V
V_IN = 1.14V to 1.26V
V_CCAUX = 2.25V to 2.75V
V_IN = 3.0V to 3.6V
V_IN = 2.3V to 2.7V
V_IN = 1.7V to 1.9V
V_IN = 1.4V to 1.6V
V_IN = 1.14V to 1.26V
All V_CCO levels
–
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
V_CCO = 3.3V ± 10%
V_CCO = 2.5V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25
–10
–
+10
Add I_HS + I_RPU
–151 –315 –710
–82 –182 –437
–36 –88 –226
–22 –56 –148
–11 –31 –83
5.1 11.4 23.9
6.2 14.8 33.1
8.4 21.6 52.6
10.8 28.4 74.0
15.3 41.1 119.4
167 346 659
100 225 457
5.5 10.4 20.8
4.1
7.8 15.7
3.0
5.7 11.1
2.7
5.1
9.6
2.4
4.5
8.1
7.9 16.0 35.0
5.9 12.0 26.3
4.2
8.5 18.6
3.6
7.2 15.7
3.0
6.0 12.5
–10
–
+10
–
–
10
90
100 115
90
110
–
Units
µA
µA
µA
µA
µA
µA
µA
µA
kΩ
kΩ
kΩ
kΩ
kΩ
µA
µA
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
µA
pF
Ω
Ω
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. For single-ended signals that are placed on a differential-capable I/O, V_IN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide.
3. This parameter is based on characterization. The pull-up resistance R_PU = V_CCO / I_RPU. The pull-down resistance R_PD = V_IN / I_RPD.
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DS529-3 (v2.0) August 19, 2010