XC3S50A-4TQG144C Datasheet, PDF (66/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
Table 57: Types of Pins on Spartan-3A FPGAs(Continued)
Type / Color
Code
Description
Pin Name(s) in Type
PWR
MGMT
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated SUSPEND, AWAKE
pin and is powered by V_CCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is
enabled in the application, AWAKE is available as a user-I/O pin.
JTAG
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has TDI, TMS, TCK, TDO
four dedicated JTAG pins. These pins are powered by VCCAUX.
GND
Dedicated ground pin. The number of GND pins depends on the package used. All must GND
be connected.
VCCAUX
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the
VCCAUX
package used. All must be connected. V_CCAUX can be either 2.5V or 3.3V. Set on board
and using CONFIG VCCAUX constraint.
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on VCCINT
the package used. All must be connected to +1.2V.
VCCO
Along with all the other VCCO pins in the same bank, this pin supplies power to the output VCCO_#
buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All
must be connected.
N.C.
This package pin is not connected in this specific device/package combination but may be N.C.
connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 58.
Table 58: Power and Ground Supply Pins by Package
Package
VCCINT VCCAUX VCCO GND
VQ100
4
3
6
13
TQ144
4
4
8
13
FT256 (50A/200A/400A)
6
4
16
28
FT256 (700A/1400A)
15
10
13
50
FG320
6
8
16
32
FG400
9
8
22
43
FG484
15
10
24
53
FG676
23
14
36
77
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 59. The table shows the
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a dual-purpose I/O pin. Likewise, the table
shows the maximum number of differential pin-pairs
available on the package. Finally, the table shows how the
total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
device.
Not all I/O standards are supported on all I/O banks. The left
and right banks (I/O banks 1 and 3) support higher output
drive current than the top and bottom banks (I/O banks 0
and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the chapter
“Using I/O Resources” in UG331.
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DS529-4 (v2.0) August 19, 2010