XC3S50A-4TQG144C Datasheet, PDF (5/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
• Master Serial from a Xilinx Platform Flash PROM
• Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
• Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
• Slave Serial, typically downloaded from a processor
• Slave Parallel, typically downloaded from a processor
• Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in Table 2.
Spartan-3A FPGAs support the following single-ended
standards:
• 3.3V low-voltage TTL (LVTTL)
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
• 3.3V PCI at 33 MHz or 66 MHz
• HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Spartan-3A FPGAs support the following differential
standards:
• LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
• Bus LVDS I/O at 2.5V
• TMDS I/O at 3.3V
• Differential HSTL and SSTL I/O
• LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package
Body Size
(mm)
Device
XC3S50A
XC3S200A
VQ100
VQG100
14 x 14⁽²⁾
User Diff
68
60
(13) (24)
68
60
(13) (24)
XC3S400A
-
-
XC3S700A
-
-
XC3S1400A -
-
TQ144
TQG144
20 x 20⁽²⁾
User Diff
108 50
(7) (24)
-
-
-
-
-
-
-
-
FT256
FTG256
17 x 17
User Diff
144 64
(32) (32)
195 90
(35) (50)
195 90
(35) (50)
161 74
(13) (36)
161 74
(13) (36)
FG320
FGG320
19 x 19
User Diff
-
-
248 112
(56) (64)
251 112
(59) (64)
-
-
-
-
FG400
FGG400
21 x 21
User Diff
-
-
-
-
311 142
(63) (78)
311 142
(63) (78)
-
-
FG484
FGG484
23 x 23
User Diff
-
-
-
-
-
-
372 165
(84) (93)
375 165
(87) (93)
FG676
FGG676
27 x 27
User Diff
-
-
-
-
-
-
-
-
502 227
(94) (131)
Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
2. The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.
DS529-1 (v2.0) August 19, 2010
www.xilinx.com
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