XC3S50A-4TQG144C Datasheet, PDF (31/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Input Timing Adjustments
Table 23: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Single-Ended Standards
LVTTL
0.62
0.62
LVCMOS33
0.54
0.54
LVCMOS25
0
0
LVCMOS18
0.83
0.83
LVCMOS15
0.60
0.60
LVCMOS12
0.31
0.31
PCI33_3
0.41
0.41
PCI66_3
0.41
0.41
HSTL_I
0.72
0.72
HSTL_III
0.77
0.77
HSTL_I_18
0.69
0.69
HSTL_II_18
0.69
0.69
HSTL_III_18
0.79
0.79
SSTL18_I
0.71
0.71
SSTL18_II
0.71
0.71
SSTL2_I
0.68
0.68
SSTL2_II
0.68
0.68
SSTL3_I
0.78
0.78
SSTL3_II
0.78
0.78
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 23: Input Timing Adjustments by IOSTANDARD(Continued)
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Differential Standards
LVDS_25
0.76
0.76
ns
LVDS_33
0.79
0.79
ns
BLVDS_25
0.79
0.79
ns
MINI_LVDS_25
0.78
0.78
ns
MINI_LVDS_33
0.79
0.79
ns
LVPECL_25
0.78
0.78
ns
LVPECL_33
0.79
0.79
ns
RSDS_25
0.79
0.79
ns
RSDS_33
0.77
0.77
ns
TMDS_33
0.79
0.79
ns
PPDS_25
0.79
0.79
ns
PPDS_33
0.79
0.79
ns
DIFF_HSTL_I_18
0.74
0.74
ns
DIFF_HSTL_II_18
0.72
0.72
ns
DIFF_HSTL_III_18
1.05
1.05
ns
DIFF_HSTL_I
0.72
0.72
ns
DIFF_HSTL_III
1.05
1.05
ns
DIFF_SSTL18_I
0.71
0.71
ns
DIFF_SSTL18_II
0.71
0.71
ns
DIFF_SSTL2_I
0.74
0.74
ns
DIFF_SSTL2_II
0.75
0.75
ns
DIFF_SSTL3_I
1.06
1.06
ns
DIFF_SSTL3_II
1.06
1.06
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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