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XC3S50A-4TQG144C Datasheet, PDF (36/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family
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DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 27 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
The Output test setup is shown in Figure 9. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an open
connection, and VT is set to zero. The same measurement
point (VM) that was used at the Input is also used at the
Output.
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
DS312-3_04_102406
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Figure 9: Output Test Setup
Table 27: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Single-Ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
Rising
Falling
PCI66_3
Rising
Falling
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
VREF (V)
-
-
-
-
-
-
-
Inputs
VL (V)
0
0
0
0
0
0
Note 3
VH (V)
3.3
3.3
2.5
1.8
1.5
1.2
Note 3
-
Note 3
Note 3
0.75
0.9
0.9
0.9
1.1
0.9
0.9
1.25
1.25
1.5
1.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.75
VREF – 0.75
VREF – 0.75
VREF – 0.75
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.75
VREF + 0.75
VREF + 0.75
VREF + 0.75
Outputs
RT (Ω)
VT (V)
1M
0
1M
0
1M
0
1M
0
1M
0
1M
0
25
0
25
3.3
25
0
25
3.3
50
0.75
50
1.5
50
0.9
25
0.9
50
1.8
50
0.9
25
0.9
50
1.25
25
1.25
50
1.5
25
1.5
Inputs and
Outputs
VM (V)
1.4
1.65
1.25
0.9
0.75
0.6
0.94
2.03
0.94
2.03
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
36
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DS529-3 (v2.0) August 19, 2010
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