XC3S50A-4TQG144C Datasheet, PDF (45/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 34: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Combinatorial Delay
T_MULT
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
Clock-to-Output Times
T_{MSCKP_P}
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register^(2,3)
T_{MSCKP_A}
T_{MSCKP_B}
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register^(2,4)
Setup Times
T_{MSDCK_P}
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)⁽³⁾
T_{MSDCK_A}
Data setup time at the A input before the active transition at the CLK
when using the AREG input register⁽⁴⁾
T_{MSDCK_B}
Data setup time at the B input before the active transition at the CLK
when using the BREG input register⁽⁴⁾
Hold Times
T_{MSCKD_P}
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)⁽³⁾
T_{MSCKD_A}
Data hold time at the A input after the active transition at the CLK
when using the AREG input register⁽⁴⁾
T_{MSCKD_B}
Data hold time at the B input after the active transition at the CLK
when using the BREG input register⁽⁴⁾
Clock Frequency
F_MULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
register⁽¹⁾
Speed Grade
-5
-4
Min
Max
Min
Max
–
4.36
–
4.88
–
0.84
–
1.30
–
4.44
–
4.97
3.56
–
3.98
–
0.00
–
0.00
–
0.00
–
0.00
–
0.00
–
0.00
–
0.35
–
0.45
–
0.35
–
0.45
–
0
280
0
250
Notes:
1. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5. The numbers in this table are based on the operating conditions set forth in Table 8.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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