XC3S50A-4TQG144C Datasheet, PDF (51/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ Frequency for the PSCLK input
(F_PSCLK)
Input Pulse Requirements
1
167
1
167
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period
40% 60% 40% 60%
Units
MHz
-
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS⁽²⁾
FINE_SHIFT_RANGE_MIN
Description
Maximum allowed number of
DCM_DELAY_STEP steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
CLKIN < 60
MHz
CLKIN ≥ 60
MHz
Minimum guaranteed delay for variable phase shifting
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
Phase Shift Amount
Units
±[INTEGER(10 • (T_CLKIN – 3 ns))] steps
±[INTEGER(15 • (T_CLKIN – 3 ns))]
±[MAX_STEPS •
ns
DCM_DELAY_STEP_MIN]
±[MAX_STEPS •
ns
DCM_DELAY_STEP_MAX]
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 40.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 37.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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