XC3S50A-4TQG144C Datasheet, PDF (91/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
FT256 Footprint (XC3S50A)
1
A GND
B TDI
2
PROG_B
3
I/O
L19P_0
(Differential Outputs)
4
5
6
7
I/O
I/O
I/O
L18P_0 L17P_0 L15P_0
N.C.
TMS
I/O
I/O _{VCCO_0} I/O
GND
L19N_0 L18N_0
L15N_0
Bank 0
8
9
I/O
L12P_0
GCLK10
I/O
L10N_0
GCLK7
(Differential Outputs)
10 11 12 13
I/O
I/O
L08N_0 L07N_0
N.C.
I/O
L04N_0
14
I/O
L04P_0
15
TCK
I/O
L12N_0 VCCO_0
GCLK11
I/O
L08P_0
GND
INPUT
VCCO_0
I/O
L02N_0
I/O
L02P_0
VREF_0
16
GND
TDO
C
I/O
L01N_3
I/O
L01P_3
GND
I/O
L20P_0
VREF_0
I/O
L17N_0
I/O
L16N_0
N.C.
I/O
L11P_0
GCLK8
I/O
L10P_0
GCLK6
I/O
L09P_0
GCLK4
I/O
L07P_0
I/O
L03P_0
I/O
L01N_0
GND
I/O
I/O
L24N_1 L24P_1
D
I/O
L03P_3
VCCO_3
I/O
L02N_3
I/O
L02P_3
I/O
L20N_0
PUDC_B
INPUT
I/O
L16P_0
I/O
L11N_0
GCLK9
I/O
L09N_0
GCLK5
N.C.
I/O _INPUT I/O
I/O
I/O
I/O
L03N_0
L01P_0 L23N_1 L22N_1 L22P_1
E
I/O
L03N_3
N.C.
N.C. ^INPUT GND INPUT N.C. VCCO_0 ^INPUT N.C. VCCAUX GND
I/O
I/O _{VCCO_1 N.C.}
L04P_3
VREF_0
L23P_1 L20P_1
F
I/O
L08P_3
GND
N.C.
INPUT
L04N_3 VCCAUX
VREF_3
GND
INPUT
N.C.
INPUT
INPUT
INPUT
L25N_1
INPUT
L25P_1
VREF_1
I/O
L20N_1
N.C.
N.C.
N.C.
I/O
I/O
G L08N_3 L11P_3
VREF_3 LHCLK0
N.C.
I/O
I/O
H L11N_3 VCCO_3 L12P_3
LHCLK1
LHCLK2
I/O
I/O
I/O
J
L14N_3
L14P_3
L12N_3
IRDY2
LHCLK5 LHCLK4 _LHCLK3
I/O
K L15N_3
LHCLK7
GND
I/O
L15P_3
TRDY2
LHCLK6
L N.C. N.C. N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C. VCCINT GND VCCINT GND
INPUT ^INPUT
L21N_1
L21P_1
VREF_1
N.C.
N.C.
GND
N.C.
N.C.
VCCO_3
N.C.
N.C.
INPUT _{VCCINT GND} INPUT
L13P_3
L13P_1
INPUT _{GND VCCINT N.C.}
L13N_3
INPUT
L13N_1
N.C.
VCCO_1
I/O
L10P_1
N.C.
I/O
L10N_1
I/O
L14N_1
RHCLK5
I/O
L14P_1
RHCLK4
I/O
L15P_1
IRDY1
RHCLK6
VCCO_1
I/O
L15N_1
RHCLK7
I/O
L12N_1
TRDY1
RHCLK3
INPUT INPUT
L21P_3 L21N_3
GND
VCCINT
GND
VCCINT ^INPUT
INPUT
L04N_1
L04P_1 _{VREF_1}
N.C.
I/O
I/O
I/O
L11N_1 L11P_1 L12P_1
RHCLK1 RHCLK0 RHCLK2
INPUT
INPUT
L25N_3
INPUT
INPUT
INPUT
INPUT
L25P_3 _{VREF_3}
VREF_2 VREF_2
GND
VCCAUX
N.C.
N.C.
GND
N.C.
M
I/O
L20P_3
VCCO_3
N.C.
I/O
L24N_3
GND VCCAUX ^{INPUT INPUT} VCCO_2 N.C.
VREF_2 VREF_2
INPUT _GND
VREF_2
N.C.
N.C.
N.C.
N.C.
N
I/O
L20N_3
P
I/O
L22N_3
R
I/O
L23P_3
T GND
I/O
L22P_3
I/O
L24P_3
I/O
L01P_2
M1
INPUT
VREF_2
I/O
L23N_3
GND
I/O
L01N_2
M0
I/O
L04N_2
VS0
I/O
L02P_2
M2
I/O
L03P_2 VCCO_2
RDWR_B
I/O
L06P_2
I/O
L02N_2
CSO_B
I/O
L04P_2
VS2
I/O
L05P_2
I/O
L05N_2
D7
I/O
L03N_2
VS1
N.C.
GND
I/O
L06N_2
D6
N.C.
I/O
L08N_2
D4
I/O
L11P_2
GCLK0
I/O
L08P_2
D5
I/O
L10P_2
GCLK14
I/O
L11N_2
GCLK1
N.C.
VCCO_2
I/O
L12P_2
GCLK2
N.C.
I/O
L10N_2
GCLK15
I/O
L12N_2
GCLK3
N.C.
I/O
L14P_2
MOSI
CSI_B
GND
I/O
L14N_2
I/O
L16N_2
N.C.
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
VCCO_1
I/O
L03N_1
I/O
L16P_2
I/O
L17N_2
D3
N.C.
GND
I/O
L02N_1
LDC0
I/O
L15N_2
DOUT
VCCO_2
I/O
L20P_2
D1
I/O
L20N_2
CCLK
I/O
L02P_1
LDC1
I/O
L15P_2
AWAKE
I/O
L17P_2
INIT_B
I/O
L18P_2
D2
I/O
L18N_2
D0
DIN/MISO
DONE
I/O
L03P_1
SUSPEND
GND
(Differential Outputs)
Bank 2
(Differential Outputs)
Figure 20: XC3S50A FT256 Package Footprint (Top View)
DS529-4_09_012009
53
I/O: Unrestricted,
general-purpose user I/O
25
DUAL: Configuration pins,
then possible user I/O
15
VREF: User I/O or input
voltage reference for bank
20
INPUT: Unrestricted,
general-purpose input pin
30
CLK: User I/O, input, or
global buffer input
16
VCCO: Output voltage
supply for bank
2
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
2
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG
port pins
6
VCCINT: Internal core
supply voltage (+1.2V)
51
N.C.: Not connected
(XC3S50A only)
28 ^{GND: Ground}
4
VCCAUX: Auxiliary supply
voltage
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
91