XC3S50A-4TQG144C Datasheet, PDF (16/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

DC and Switching Characteristics
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
V_CCO for Drivers⁽²⁾
Min (V) Nom (V) Max (V)
Min (V)
V_REF
Nom (V)
Max (V)
V_IL
Max (V)
V_IH
Min (V)
LVTTL
LVCMOS33⁽⁴⁾
LVCMOS25^(4,5)
3.0
3.3
3.6
3.0
3.3
3.6
2.3
2.5
2.7
0.8
2.0
0.8
2.0
0.7
1.7
LVCMOS18
LVCMOS15
1.65
1.8
1.95
1.4
1.5
1.6
V_REF is not used for
these I/O standards
0.4
0.8
0.4
0.8
LVCMOS12
1.1
1.2
1.3
0.4
0.7
PCI33_3⁽⁶⁾
PCI66_3⁽⁶⁾
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
3.0
3.3
3.6
0.3 • V_CCO
0.5 • V_CCO
3.0
3.3
3.6
0.3 • V_CCO
0.5 • V_CCO
1.4
1.5
1.6
0.68
0.75
0.9
V_REF – 0.1
V_REF + 0.1
1.4
1.5
1.6
–
0.9
-
V_REF – 0.1
V_REF + 0.1
1.7
1.8
1.9
0.8
0.9
1.1
V_REF – 0.1
V_REF + 0.1
1.7
1.8
1.9
–
0.9
–
V_REF – 0.1
V_REF + 0.1
1.7
1.8
1.9
–
1.1
–
V_REF – 0.1
V_REF + 0.1
1.7
1.8
1.9
0.833
0.900
0.969
V_REF – 0.125 V_REF + 0.125
1.7
1.8
1.9
0.833
0.900
0.969
V_REF – 0.125 V_REF + 0.125
2.3
2.5
2.7
1.13
1.25
1.38
V_REF – 0.150 V_REF + 0.150
2.3
2.5
2.7
1.13
1.25
1.38
V_REF – 0.150 V_REF + 0.150
3.0
3.3
3.6
1.3
1.5
1.7
V_REF – 0.2
V_REF + 0.2
3.0
3.3
3.6
1.3
1.5
1.7
V_REF – 0.2
V_REF + 0.2
Notes:
1. Descriptions of the symbols used in this table are as follows:
V_CCO – the supply voltage for output drivers
V_REF – the reference voltage for setting the input switching threshold
V_IL – the input voltage that indicates a Low logic level
V_IH – the input voltage that indicates a High logic level
2. In general, the V_CCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when V_CCAUX = 3.3V range
and for PCI I/O standards.
3. For device operation, the maximum signal voltage (V_IH max) can be as high as V_IN max. See Table 8.
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V_CCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on V_CCAUX. The dual-purpose configuration pins use the LVCMOS standard before the User mode. When
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V_CCO lines of Banks 0, 1, and 2 at power-on as well as
throughout configuration.
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
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DS529-3 (v2.0) August 19, 2010