XC3S50A-4TQG144C Datasheet, PDF (87/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
User I/Os by Bank
Table 70, Table 71, and Table 72 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FT256 package. The AWAKE pin is counted as a
dual-purpose I/O.
The XC3S50A FPGA in the FT256 package has 51
unconnected balls, labeled with an “N.C.” type. These pins
are also indicated in Figure 20.
Table 70: User I/Os Per Bank on XC3S50A in the FT256 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
40
21
7
1
3
Right
1
32
12
5
4
3
Bottom
2
40
5
2
21
6
Left
3
32
15
6
0
3
TOTAL
144
53
20
26
15
CLK
8
8
6
8
30
.
Table 71: User I/Os Per Bank on XC3S200A and XC3S400A in the FT256 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
47
27
6
1
5
Right
1
50
1
6
30
5
Bottom
2
48
11
2
21
6
Left
3
50
30
7
0
5
TOTAL
195
69
21
52
21
CLK
8
8
8
8
32
Table 72: User I/Os Per Bank on XC3S700A and XC3S1400A in the FT256 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
41
27
1
1
4
Right
1
40
0
0
30
4
Bottom
2
41
7
0
21
5
Left
3
39
25
1
0
5
TOTAL
161
59
2
52
18
CLK
8
6
8
8
30
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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