XC3S50A-4TQG144C Datasheet, PDF (131/132 Pages) Xilinx, Inc – Spartan-3A FPGA Family

Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
12/05/06
02/02/07
03/16/07
04/23/07
05/08/07
07/10/07
04/15/08
05/28/08
03/06/09
08/19/10
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.0
Revision
Initial release.
Promoted to Preliminary status. Added DOUT pin to DUAL-type pins in Table 57. Corrected counts for
DUAL pins and differential pairs in Table 59. Corrected minor typographical error on pin names for pin
numbers P24 and P25 in Table 66. Highlighted the differences in differential I/O pairs between the
XC3S50A and XC3S200A in the FT256 package, shown in Table 68 and added Table 74 and Table 75
to summarize the differences.
Corrected minor typographical error in Figure 19.
Added reference to compatible Spartan-3A DSP family.
Added note regarding banking rules.
Updated Thermal Characteristics in Table 62.
Added VQ100 for XC3S50A and XC3S200A and added FT256 for XC3S700A and XCS1400A to
Table 58, Table 59, and Table 62. Updated Thermal Characteristics with latest data in Table 62.
Corrected bank for T8 and type for U16 in Table 86. Removed VREF name on 6 unconnected N.C. pins
for XC3S1400A FG676 in Table 87 and Figure 27. These pins are noted as VREF if migrating up to the
XC3SD1800A in Table 89.
Added "Package Overview" section.
Corrected bank designation for SUSPEND to VCCAUX. Corrected bank designation for JTAG pins in
XC3S700A and XC3S1400A FT256 to VCCAUX.
Corrected pin 36 number in Figure 17 and Figure 18. Noted difference in FT256 P10/T10 function
between XC3S50A and larger devices in Table 68 and Table 74.
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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