XC3S50A-4FTG256C Datasheet, PDF (93/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

FT256 Footprint (XC3S700A, XC3S1400A)
Pinout Descriptions
Bank 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
A
GND
PROG_B
I/O
L19P_0
I/O
L18P_0
I/O
L17P_0
I/O
L15P_0
I/O
L13P_0
I/O
L12P_0
I/O
L10N_0
I/O
L08N_0
I/O
L07N_0
I/O
L05N_0
I/O
L04N_0
I/O
L04P_0
TCK
GCLK10 GCLK7
GND
B ^TDI
TMS
I/O
L19N_0
I/O
L18N_0
VCCO_0
I/O
L15N_0
GND
I/O
L12N_0
GCLK11
VCCO_0
I/O
L08P_0
GND
I/O
L05P_0
VCCO_0
I/O
L02N_0
I/O
L02P_0
VREF_0
TDO
C
I/O
I/O
L01N_3 L01P_3
GND
I/O
L20P_0
VREF_0
I/O
L17N_0
I/O
L16N_0
I/O
L13N_0
I/O
L11P_0
GCLK8
I/O
L10P_0
GCLK6
I/O
L09P_0
GCLK4
I/O
L07P_0
I/O
L03P_0
I/O
L01N_0
GND
I/O
I/O
L24N_1 L24P_1
A25 A24
D
I/O
L03P_3
VCCO_3
I/O
L02N_3
I/O
L02P_3
I/O
L20N_0 VCCAUX
PUDC_B
I/O
L16P_0
I/O
L11N_0
GCLK9
I/O
L09N_0
GCLK5
I/O
L06N_0
VREF_0
I/O
L06P_0
I/O
L03N_0
I/O
L01P_0
I/O
L23N_1
A23
I/O
L22N_1
A21
I/O
L22P_1
A20
E
I/O
I/O
I/O
I/O
L03N_3 L05N_3 L05P_3 L04P_3
GND
INPUT
I/O
L14N_0
VREF_0
VCCO_0
I/O
L14P_0
GND VCCAUX GND
I/O
I/O
I/O
L23P_1 L20P_1 VCCO_1 L18P_1
A22
A18
A14
F
I/O
L08P_3
GND
I/O
L07P_3
I/O
L04N_3
VCCAUX
GND
GND
GND
I/O
I/O
I/O
I/O
GND VCCINT GND VCCAUX L20N_1 L19N_1 L18N_1 L16N_1
A19
A17
A15
A11
G
I/O
L08N_3
VREF_3
I/O
L11P_3
LHCLK0
I/O
L07N_3
INPUT
VREF_3
GND
GND
VCCINT
GND
VCCINT
GND
VCCINT
GND
I/O
I/O
L19P_1 L17N_1
A16
A13
GND
I/O
L16P_1
A10
I/O
I/O
H ^{L11N_3 VCCO_3 L12P_3 VCCAUX GND}
LHCLK1
LHCLK2
VCCINT
GND
VCCINT
GND
VCCINT
GND
INPUT
VREF_1
I/O
L17P_1
A12
VCCAUX
I/O
L15P_1
IRDY1
RHCLK6
I/O
L15N_1
RHCLK7
J
I/O
L14N_3
LHCLK5
I/O
L14P_3
LHCLK4
I/O
L12N_3
IRDY2
LHCLK3
INPUT
INPUT
VREF_3
GND
VCCINT
GND
VCCINT
GND
VCCINT
I/O
L10P_1
A8
I/O
L10N_1
A9
I/O
INPUT
VREF_1
VCCO_1
L12N_1
TRDY1
RHCLK3
I/O
K ^L15N_3
LHCLK7
GND
I/O
L15P_3 I/O
TRDY2 L18P_3
LHCLK6
GND
VCCINT
GND
VCCINT
GND
VCCINT
GND
GND
I/O
I/O
I/O
I/O
L06N_1 L11N_1 L11P_1 L12P_1
A3 RHCLK1 RHCLK0 RHCLK2
L
I/O
L16P_3
VREF_3
I/O
L16N_3
I/O
L18N_3
I/O
L19N_3
VCCAUX
GND
VCCINT
GND
VCCINT
GND
I/O
I/O
GND VCCAUX L06P_1 L08P_1
A2
A6
GND
I/O
L08N_1
A7
M
I/O
L20P_3
VCCO_3
I/O
L19P_3
I/O
L24N_3
GND
VCCAUX
INPUT
VREF_2
GND
INPUT
VREF_2
VCCAUX
INPUT
VREF_2
GND
INPUT INPUT
VREF_1 VREF_1
I/O
L07P_1
A4
I/O
L07N_1
A5
N
I/O
L20N_3
I/O
L22P_3
VREF_3
I/O
L24P_3
I/O
L01P_2
M1
INPUT
VREF_2
I/O
L04P_2
VS1
GND
I/O
I/O
L08N_2 L11P_2
D4 GCLK0
GND
I/O
L16N_2
I/O
L19P_2
I/O
L01P_1
HDC
I/O
I/O
L01N_1 VCCO_1 L03N_1
LDC2
A1
P
I/O
I/O
L22N_3 L23N_3
GND
I/O
L01N_2
M0
I/O
L04N_2
VS0
INPUT
VREF_2
I/O
L08P_2
D5
I/O
L10P_2
GCLK14
I/O
L11N_2
GCLK1
I/O
L14N_2
MOSI
CSI_B
I/O
L16P_2
I/O
L17N_2
D3
I/O
L19N_2
GND
I/O
I/O
L02N_1 L03P_1
LDC0 A0
R
I/O
L23P_3
I/O
L02P_2
M2
I/O
L03P_2 VCCO_2
RDWR_B
I/O
L05N_2
GND
I/O
I/O
L09P_2 VCCO_2 L12P_2
GCLK12
GCLK2
GND
I/O
I/O
I/O
I/O
L15N_2 VCCO_2 L18N_2 L20N_2 L02P_1
DOUT
D1 CCLK LDC1
SUSPEND
T
GND
I/O
L02N_2
CSO_B
I/O
L03N_2
VS2
I/O
L05P_2
I/O
L06P_2
D7
I/O
L06N_2
D6
I/O
I/O
L09N_2 L10N_2
GCLK13 GCLK15
I/O
L12N_2
GCLK3
I/O
L14P_2
I/O
L15P_2
AWAKE
I/O
L17P_2
INIT_B
I/O
L18P_2
D2
I/O
L20P_2
D0/DIN
MISO
DONE
GND
Bank 2
DS529-4_012009
Figure 22: XC3S700A and XC3S1400A FT256 Package Footprint (Top View)
59
I/O: Unrestricted,
general-purpose user I/O
51
DUAL: Configuration, then
possible user I/O
18
VREF: User I/O or input
voltage reference for bank
2
INPUT: Unrestricted,
general-purpose input pin
30
CLK: User I/O, input, or
global buffer input
13
VCCO: Output voltage
supply for bank
2
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
2
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG
port pins
15
VCCINT: Internal core
supply voltage (+1.2V)
0 ^{N.C.: Not connected}
50 ^{GND: Ground}
10
VCCAUX: Auxiliary supply
voltage
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
93