XC3S50A-4FTG256C Datasheet, PDF (12/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Power Supply Specifications
Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
V_CCINTT
V_CCAUXT
V_CCO2T
Threshold for the V_CCINT supply
Threshold for the V_CCAUX supply
Threshold for the V_CCO Bank 2 supply
0.4
1.0
V
1.0
2.0
V
1.0
2.0
V
Notes:
1. V_CCINT, V_CCAUX, and V_CCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply V_CCINT last for lowest overall power consumption (see UG331 chapter “Powering Spartan-3 Generation FPGAs” for more
information).
2. To ensure successful power-on, V_CCINT, V_CCO Bank 2, and V_CCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
V_CCINTR
V_CCAUXR
V_CCO2R
Ramp rate from GND to valid V_CCINT supply level
Ramp rate from GND to valid V_CCAUX supply level
Ramp rate from GND to valid V_CCO Bank 2 supply level
0.2
100
ms
0.2
100
ms
0.2
100
ms
Notes:
1. V_CCINT, V_CCAUX, and V_CCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply V_CCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more
information).
2. To ensure successful power-on, V_CCINT, V_CCO Bank 2, and V_CCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM
Data
Symbol
Description
Min
Units
V_DRINT
V_DRAUX
V_CCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
V_CCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
2.0
V
12
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DS529-3 (v2.0) August 19, 2010