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XC3S50A-4FTG256C Datasheet, PDF (17/132 Pages) Xilinx, Inc – Architectural and Configuration Overview | |||
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DC and Switching Characteristics
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Conditions
Logic Level
Characteristics
IOSTANDARD
Attribute
LVTTL(3)
2
IOL IOH
(mA) (mA)
2 â2
VOL
Max (V)
0.4
VOH
Min (V)
2.4
4
4 â4
6
6 â6
8
8 â8
12 12 â12
16 16 â16
24 24 â24
LVCMOS33(3) 2
4
2 â2
4 â4
0.4
VCCO â 0.4
6
6 â6
8
8 â8
12 12 â12
16 16 â16
24(4) 24 â24
LVCMOS25(3) 2
4
2 â2
4 â4
0.4
VCCO â 0.4
6
6 â6
8
8 â8
12 12 â12
16(4) 16 â16
24(4) 24 â24
LVCMOS18(3) 2
4
2 â2
4 â4
0.4
VCCO â 0.4
6
6 â6
8
8 â8
12(4) 12 â12
16(4) 16 â16
LVCMOS15(3) 2
4
2 â2
4 â4
0.4
VCCO â 0.4
6
6 â6
8(4)
8
â8
12(4) 12 â12
LVCMOS12(3) 2
2 â2
4(4)
4
â4
0.4
VCCO â 0.4
6(4)
6
â6
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards(Continued)
Test
Conditions
Logic Level
Characteristics
IOSTANDARD
Attribute
PCI33_3(5)
PCI66_3(5)
HSTL_I(4)
HSTL_III(4)
HSTL_I_18
HSTL_II_18(4)
HSTL_III_18
SSTL18_I
SSTL18_II(4)
SSTL2_I
SSTL2_II(4)
SSTL3_I
SSTL3_II
IOL IOH
VOL
(mA) (mA) Max (V)
VOH
Min (V)
1.5 â0.5 10% VCCO 90% VCCO
1.5 â0.5 10% VCCO 90% VCCO
8 â8
0.4
VCCO - 0.4
24 â8
0.4
VCCO - 0.4
8 â8
0.4
VCCO - 0.4
16 â16
0.4
VCCO - 0.4
24 â8
0.4
VCCO - 0.4
6.7 â6.7 VTT â 0.475 VTT + 0.475
13.4 â13.4 VTT â 0.603 VTT + 0.603
8.1
16.2
8
16
â8.1
â16.2
â8
â16
VTT â 0.61
VTT â 0.81
VTT â 0.6
VTT â 0.8
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
2. Descriptions of the symbols used in this table are as follows:
â IOL the output current condition under which VOL is tested
â IOH the output current condition under which VOH is tested
â VOL the output voltage that indicates a Low logic level
â VOH the output voltage that indicates a High logic level
â VCCO the supply voltage for output drivers
â VTT the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
5. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
17
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