XC3S50A-4FTG256C Datasheet, PDF (44/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 33: Clock Distribution Switching Characteristics
Description
Symbol Minimum
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
T_GIO
–
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
T_GSI
–
Frequency of signals distributed on global buffers (all sides)
F_BUFG
0
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Maximum
Speed Grade
-5
-4
0.22
0.23
0.56
0.63
350
334
Units
ns
ns
MHz
44
www.xilinx.com
DS529-3 (v2.0) August 19, 2010