XC3S50A-4FTG256C Datasheet, PDF (30/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Symbol
T_IOPLID
Description
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
Conditions
LVCMOS25⁽²⁾
DELAY_VALUE
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Speed Grade
-5
-4
Device Max Max Units
XC3S400A 3.55 4.18 ns
4.34 5.03 ns
5.09 5.88 ns
5.58 6.42 ns
XC3S700A 1.96 2.18 ns
2.76 3.06 ns
3.45 3.95 ns
3.97 4.54 ns
3.83 4.37 ns
4.74 5.42 ns
5.53 6.33 ns
6.06 6.96 ns
XC3S1400A 1.93 2.40 ns
2.69 3.15 ns
3.52 3.99 ns
3.89 4.55 ns
3.95 4.42 ns
4.53 5.32 ns
5.30 6.21 ns
5.83 6.80 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 23.
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DS529-3 (v2.0) August 19, 2010