XC3S50A-4FTG256C Datasheet, PDF (52/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Miscellaneous DCM Timing
Table 42: Miscellaneous DCM Timing
Symbol
Description
Min
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
DCM_RST_PW_MAX⁽²⁾
DCM_CONFIG_LAG_TIME⁽³⁾
Maximum duration of a RST pulse width
N/A
N/A
Maximum duration from V_CCINT applied to FPGA configuration
N/A
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
N/A
Max
Units
–
CLKIN
cycles
N/A
seconds
N/A
seconds
N/A
minutes
N/A
minutes
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
DNA Port Timing
Table 43: DNA_PORT Interface Timing
Symbol
Description
T_DNASSU
T_DNASH
T_DNADSU
T_DNADH
T_DNARSU
T_DNARH
T_DNADCKO
T_DNACLKF
T_DNACLKH
T_DNACLKL
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
CLK High time
CLK Low time
Notes:
1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
2. The numbers in this table are based on the operating conditions set forth in Table 8.
Min
Max
Units
1.0
–
ns
0.5
–
ns
1.0
–
ns
0.5
–
ns
5.0
10,000
ns
0
–
ns
0.5
1.5
ns
0
100
MHz
1.0
∞
ns
1.0
∞
ns
52
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DS529-3 (v2.0) August 19, 2010